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coreboot-kgpe-d16/src/mainboard/google/kukui/Makefile.inc

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google/kukui: Initialize DRAM from romstage Add DRAM support for google kukui. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1ed01404343745c883b22a648966327bdcabc5c2 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-13 10:20:00 +02:00
subdirs-y += sdram_params/
mb/google/kukui: Move panel description to CBFS files The panel description may be pretty large (for example, 1.3k for BOE TV101) due to init commands and we should only load the right config when display is needed. BUG=None TEST=make -j; boots and see display on Krane. Change-Id: I2560a11ecf7badfd0605ab189d57ec9456850f75 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15 03:43:55 +02:00
subdirs-y += panel_params/
google/kukui: Initialize DRAM from romstage Add DRAM support for google kukui. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1ed01404343745c883b22a648966327bdcabc5c2 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-13 10:20:00 +02:00
google/kukui: Add SPI NOR support This patch sets SPI flash related configs and inits SPI bus 1 to support SPI NOR flash. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-06 09:37:05 +02:00
bootblock-y += bootblock.c
google/kukui: Implement HW reset function Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 06:28:14 +01:00
bootblock-y += reset.c
google/kukui: Add MediaTek MT8183 reference board BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 03:22:53 +02:00
verstage-y += chromeos.c
google/kukui: Move some initialization from bootblock to verstage MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-29 13:04:59 +01:00
verstage-y += early_init.c
google/kukui: Implement HW reset function Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 06:28:14 +01:00
verstage-y += reset.c
google/kukui: Support TPM Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ, implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM interrupt. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-19 11:29:23 +02:00
verstage-y += verstage.c
google/kukui: Add MediaTek MT8183 reference board BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 03:22:53 +02:00
google/kukui: Add board id support Get board id from AUXIN4 and RAM code from AUXIN3. BUG=b:80501386 BRANCH=none TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0. AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1. Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-12 07:27:15 +02:00
romstage-y += boardid.c
google/kukui: Add MediaTek MT8183 reference board BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 03:22:53 +02:00
romstage-y += chromeos.c
google/kukui: Move some initialization from bootblock to verstage MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-29 13:04:59 +01:00
romstage-y += early_init.c
google/kukui: Implement HW reset function Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 06:28:14 +01:00
romstage-y += reset.c
google/kukui: Add MediaTek MT8183 reference board BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 03:22:53 +02:00
romstage-y += romstage.c
google/kukui: Initialize DRAM from romstage Add DRAM support for google kukui. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1ed01404343745c883b22a648966327bdcabc5c2 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/28438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-13 10:20:00 +02:00
romstage-y += sdram_configs.c
google/kukui: Add MediaTek MT8183 reference board BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 03:22:53 +02:00
google/kukui: Add board id support Get board id from AUXIN4 and RAM code from AUXIN3. BUG=b:80501386 BRANCH=none TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0. AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1. Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-12 07:27:15 +02:00
ramstage-y += boardid.c
google/kukui: Add MediaTek MT8183 reference board BUG=b:80501386 BRANCH=none TEST=timer and uart work fine Change-Id: I08644892d34925574f791b000b0035d5afad7022 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26722 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 03:22:53 +02:00
ramstage-y += chromeos.c
google/kukui: Update MMU table in romstage and ramstage In order to get better performance, map dram as cached after dram ready in romstage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Need a futher check after dram calibration code ready. Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27304 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-19 10:07:54 +02:00
ramstage-y += mainboard.c
mb/google/kukui: Add flapjack panels Add panels supported by flapjack. Change-Id: I547bf6f26bdbfed52a00c8cfb268d4e7c17ed889 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-16 05:54:21 +02:00
ramstage-$(CONFIG_BOARD_GOOGLE_FLAPJACK) += panel_flapjack.c
mb/google/kukui: Add panel for Kakadu Declare the following panel for Kakadu: - BOE_TV105WUM_NW0 BUG=b:148997748 TEST=build Kakadu image passed BRANCH=kukui Signed-off-by: Casper Chang <casper_chang@bitand.corp-partner.google.com> Change-Id: I394b8cafa8be40e5fd6bf8ceb81b520df73718a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38822 Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11 04:34:26 +01:00
ramstage-$(CONFIG_BOARD_GOOGLE_KAKADU) += panel_kakadu.c
mb/google/kukui: Add panel for Katsu Declare the following panel for Katsu: - BOE_TV105WUM_NW0 - STA_2081101QFH032011_53G BUG=b:176523929 TEST=build Katsu image passed BRANCH=kukui Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-22 11:16:13 +01:00
ramstage-$(CONFIG_BOARD_GOOGLE_KATSU) += panel_katsu.c
mb/google/kukui: Add panel for Kodama Declare the following panel for Kodama: - BOE TV101WUM-N53 BUG=b:138156559 TEST=builds Kodama image and working properly Change-Id: I129cb6bf084b76da3ad33b7a19e38e884442b1aa Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34505 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-23 05:42:49 +02:00
ramstage-$(CONFIG_BOARD_GOOGLE_KODAMA) += panel_kodama.c
mb/google/kukui: Add panels for Krane Declare the following panels for Krane: - BOE TV101WUM-NL6 - AUO KD101N80-45NA The edid info and init command are from: https://crrev.com/c/1565758 BUG=b:129299873 BRANCH=none TEST=Builds krane image and boots properly. Change-Id: Id19c6c2b4c1c728c39aa26301adf7d6fb5046403 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-29 12:20:53 +02:00
ramstage-$(CONFIG_BOARD_GOOGLE_KRANE) += panel_krane.c
mb/google/kukui: Add panel for Kukui Support Kukui rev 2 panel (via SSD2858). BUG=b:129299873 BRANCH=none TEST=Build as Kukui and boots on Rev 2 unit. Change-Id: Icc16c4297eb3c6b6a4770a36661a2e3cab418048 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-20 06:04:59 +02:00
ramstage-$(CONFIG_BOARD_GOOGLE_KUKUI) += panel_kukui.c
mb/google/kukui: Support eDP panels via PS8640 Some Kukui variants may have eDP panels connected via a PS8640 MIPI bridge which we may retrieve EDID dynamically. BUG=b:b:137517228 TEST=emerge-jacuzzi coreboot chromeos-bootimage; boots and see display. Change-Id: I85aac5255e6a3e6019299670486214ecffbf9801 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34516 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 11:09:53 +02:00
ramstage-$(CONFIG_DRIVER_PARADE_PS8640) += panel_ps8640.c
mb/google/kukui: Support panels using ANX7625 For Kukui followers using ANX7625 eDP bridge to access panel. BUG=b:140132295 TEST=make # board = kukui Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-12 08:04:26 +01:00
ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c
google/kukui: Implement HW reset function Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 06:28:14 +01:00
ramstage-y += reset.c
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