coreboot-kgpe-d16/src/mainboard/intel/dg43gt/cstates.c

/* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpigen.h>

int get_cst_entries(acpi_cstate_t **entries)
{
	return 0;
}
mainboard/intel: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I1ea2eebfdd43610e42b4cf04409ec76c2e8b0042 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> 2020-04-03 01:22:13 +02:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
mb/intel/dg43gt: Add mainboard This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash. What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA with AHCI * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * VGA (on DVI) with NGI if patched to use DVI gmbus port for output * PCI * Reboot and S3 resume * Descriptor mode with ME disable straps and ME region absent (no working gbe in this configuration though) * USB. What does not work: * GBE (probably requires working ME); * Analog on DVI port out is shaking, which is not the case with vendor BIOS (setting clockgen on smbus 0x69 like vendor fixes it). * Booting with ME enabled (needs raminit patches for that) Not tested: * Sound; * All the rest. Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible. TESTED with SeaBIOS and Linux 4.10.8 Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> 2017-04-12 13:53:08 +02:00
acpi: Move ACPI table support out of arch/x86 (3/5) This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" \| xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> 2020-05-02 19:24:23 +02:00			`#include <acpi/acpigen.h>`
mb/intel/dg43gt: Add mainboard This mainboard features is an G43 northbridge, ICH10 southbridge and Winbond W83627dhg SuperI/O. This board is impossible to flash internally with vendor bios (BIOS region is WP and other regions like IFD and ME are read only and inaccessible respectively). Due to either ICH10 or board layout it is also impossible to do ISP, which requires desoldering flash chip. To make hacking more easy there is an empty SPI header next to spi flash pads which can be hooked up to a SPI flash. What works: * 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1); * SATA with AHCI * Integrated GPU with option rom (extracted from a Gigabyte vendor bios) * VGA (on DVI) with NGI if patched to use DVI gmbus port for output * PCI * Reboot and S3 resume * Descriptor mode with ME disable straps and ME region absent (no working gbe in this configuration though) * USB. What does not work: * GBE (probably requires working ME); * Analog on DVI port out is shaking, which is not the case with vendor BIOS (setting clockgen on smbus 0x69 like vendor fixes it). * Booting with ME enabled (needs raminit patches for that) Not tested: * Sound; * All the rest. Not coreboot related problems: * Flashing this board with vendor bios is a PITA and requires desoldering flash chip; * In situ programming is not possible. TESTED with SeaBIOS and Linux 4.10.8 Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> 2017-04-12 13:53:08 +02:00
			`int get_cst_entries(acpi_cstate_t **entries)`
			`{`
			`return 0;`
			`}`