2013-08-13 11:09:51 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Memory related values */
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Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
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Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
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Name(PBLN, 0x0) /* Length of BIOS area */
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Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
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Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
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Name(HPBA, 0xFED00000) /* Base address of HPET table */
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/* Some global data */
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2014-05-31 05:57:52 +02:00
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Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
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2013-08-13 11:09:51 +02:00
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Name(OSV, Ones) /* Assume nothing */
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Name(PMOD, One) /* Assume APIC */
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2013-11-21 09:12:27 +01:00
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/* AcpiGpe0Blk */
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OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
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Field(GP0B, ByteAcc, NoLock, Preserve) {
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, 11,
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USBS, 1,
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}
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