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coreboot-kgpe-d16/Documentation/releases/coreboot-4.11-relnotes.md

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Documentation: Add 4.10/4.11 release notes For 4.11 that's obviously just the release notes template. Change-Id: I44c15bcaedf1367d745c533cc0a4acebdd2f812e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-07-21 12:57:18 +02:00
Upcoming release - coreboot 4.11
================================
The 4.11 release is planned for October 2019
Update this document with changes that should be in the release
notes.
* Please use Markdown.
* See the [4.9](coreboot-4.9-relnotes.md) and [4.10](coreboot-4.10-relnotes.md)
release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
Documentation/releases: Note pending AMD fam12h removal Change-Id: I386572c772ea9de571bbb9d51ef9090e9c429b99 Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-28 14:43:30 +01:00
Clean Up
--------
Because there was only a single developer board (AMD Torpedo)
using AGESA family 12h, and because there were multiple,
unique Coverity issues with it, the associated vendorcode will
be removed shortly after this release.
Documentation: Add 4.10/4.11 release notes For 4.11 that's obviously just the release notes template. Change-Id: I44c15bcaedf1367d745c533cc0a4acebdd2f812e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-07-21 12:57:18 +02:00
Significant changes
-------------------
### Add significant changes here
Documentation: Add some significant 4.11 release notes Change-Id: I44369bc7dee77beab480d9a16cd7268be6686eb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2019-11-02 10:12:09 +01:00
### `__PRE_RAM__` is deprecated
Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with
`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`.
The remaining cases and `-D__PRE_RAM__` are to be removed soon after release.
### `CAR_GLOBAL` is removed where possible
For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL`
attributes have been removed. Remaining cases from common code are to be
removed soon after release.
### `TSEG` and `cbmem_top()` mapping
Significant refactoring has bee done to achieve some consistency across platforms
and to reduce code duplication.
Documentation: Add some significant 4.11 release notes Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-05 08:32:19 +01:00
### Added VBOOT support to the following platforms:
* intel/gm45
* intel/nehalem
### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK:
* intel/gm45
* intel/nehalem
* intel/braswell
### Other
* Did cleanups around TSC timer
* Improved automatic VR configuration on SKL/KBL
* Filled additional fields in SMBIOS type 4
* Removed magic value replay from Intel Nehalem/ibexpeak code base
* Added OpenSBI on RISCV platforms
* Did more preparations for Intel TXT support
* Did more preparations for x86_64 stage support
* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb