57 lines
1.4 KiB
Text
57 lines
1.4 KiB
Text
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, // DSDT revision: ACPI v5.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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// Some generic macros
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#include <soc/intel/skylake/acpi/platform.asl>
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// global NVS and variables
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#include <soc/intel/skylake/acpi/globalnvs.asl>
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// CPU
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#include <soc/intel/skylake/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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}
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// Dynamic Platform Thermal Framework
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#include "acpi/dptf.asl"
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}
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// Chrome OS specific
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#include "acpi/chromeos.asl"
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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// Chipset specific sleep states
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#include <soc/intel/skylake/acpi/sleepstates.asl>
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// Mainboard specific
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#include "acpi/mainboard.asl"
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}
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