184 lines
4.7 KiB
C
184 lines
4.7 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _FSP_BAYTRAIL_CHIP_H_
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#define _FSP_BAYTRAIL_CHIP_H_
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#include <arch/acpi.h>
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/* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree. */
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struct soc_intel_fsp_baytrail_config {
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/* ***** UPD Configuration ***** */
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/* Spd addresses */
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uint8_t MrcInitSPDAddr1;
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uint8_t MrcInitSPDAddr2;
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#define SPD_ADDR_DEFAULT 0x00
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#define SPD_ADDR_DISABLED 0xFF
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/* SataMode
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* NOTE: These are offset by 1 to set 0 as "use default". This is so that
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* if the register value is not set in the devicetree.cb file, the default
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* value gets used. This is fixed up in the chipset_fsp_util.c code.
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*
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* 0x0 "IDE"
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* 0x1 "AHCI"
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*/
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uint8_t SataMode;
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#define SATA_MODE_DEFAULT 0x00
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#define SATA_MODE_IDE 0x01
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#define SATA_MODE_AHCI 0x02
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/*
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* MrcInitTsegSize
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* 0x01, "1 MB"
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* 0x02, "2 MB"
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* 0x04, "4 MB"
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* 0x08, "8 MB"
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*/
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uint16_t MrcInitTsegSize;
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#define TSEG_SIZE_DEFAULT 0
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#define TSEG_SIZE_1_MB 1
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#define TSEG_SIZE_2_MB 2
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#define TSEG_SIZE_4_MB 4
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#define TSEG_SIZE_8_MB 8
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/*
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* MrcInitMmioSize
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* 0x400, "1.0 GB"s
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* 0x600, "1.5 GB"
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* 0x800, "2.0 GB"
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*/
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uint16_t MrcInitMmioSize;
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#define MMIO_SIZE_DEFAULT 0x00
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#define MMIO_SIZE_1_0_GB 0x400
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#define MMIO_SIZE_1_5_GB 0x600
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#define MMIO_SIZE_2_0_GB 0x800
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/*
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* eMMCBootMode
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* NOTE: These are offset by 1 to set 0 as "use default". This is so that
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* if the register value is not set in the devicetree.cb file, the default
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* value gets used. This is fixed up in the chipset_fsp_util.c code
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*
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* 0x0 "Disabled"
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* 0x1 "Auto"
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* 0x2 "eMMC 4.1"
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* 0x3 "eMMC 4.5"
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*/
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uint8_t eMMCBootMode;
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#define EMMC_USE_DEFAULT 0
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#define EMMC_DISABLED 1
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#define EMMC_AUTO 2
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#define EMMC_4_1 3
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#define EMMC_4_5 4
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#define EMMC_FOLLOWS_DEVICETREE 5
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/*
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* IgdDvmt50PreAlloc
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* 0x01, "32 MB"
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* 0x02, "64 MB"
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* 0x03, "96 MB"
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* 0x04, "128 MB"
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* 0x05, "160 MB"
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* 0x06, "192 MB"
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* 0x07, "224 MB"
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* 0x08, "256 MB"
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* 0x09, "288 MB"
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* 0x0A, "320 MB"
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* 0x0B, "352 MB"
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* 0x0C, "384 MB"
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* 0x0D, "416 MB"
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* 0x0E, "448 MB"
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* 0x0F, "480 MB"
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* 0x10, "512 MB"
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*/
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uint8_t IgdDvmt50PreAlloc;
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#define IGD_MEMSIZE_DEFAULT 0x00
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#define IGD_MEMSIZE_32MB 0x01
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#define IGD_MEMSIZE_64MB 0x02
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#define IGD_MEMSIZE_96MB 0x03
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#define IGD_MEMSIZE_128MB 0x04
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#define IGD_MEMSIZE_160MB 0x05
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#define IGD_MEMSIZE_192MB 0x06
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#define IGD_MEMSIZE_224MB 0x07
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#define IGD_MEMSIZE_256MB 0x08
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#define IGD_MEMSIZE_288MB 0x09
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#define IGD_MEMSIZE_320MB 0x0A
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#define IGD_MEMSIZE_352MB 0x0B
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#define IGD_MEMSIZE_384MB 0x0C
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#define IGD_MEMSIZE_416MB 0x0D
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#define IGD_MEMSIZE_448MB 0x0E
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#define IGD_MEMSIZE_480MB 0x0F
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#define IGD_MEMSIZE_512MB 0x10
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#define IGD_MEMSIZE_MULTIPLIER 32
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/*
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* Selection 0x1 , "128 MB"
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* Selection 0x2 , "256 MB"
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* Selection 0x3 , "512 MB"
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*/
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uint8_t ApertureSize;
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#define APERTURE_SIZE_DEFAULT 0
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#define APERTURE_SIZE_128MB 1
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#define APERTURE_SIZE_256MB 2
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#define APERTURE_SIZE_512MB 3
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#define APERTURE_SIZE_BASE 64
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/*
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* Selection 0x1 , "1 MB"
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* Selection 0x2 , "2 MB"
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*/
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uint8_t GttSize;
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#define GTT_SIZE_DEFAULT 0
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#define GTT_SIZE_1MB 1
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#define GTT_SIZE_2MB 2
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/*
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* Enable PCI Mode for LPSS SIO devices.
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* If disabled, LPSS SIO devices will run in ACPI mode.
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*/
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uint8_t LpssSioEnablePciMode;
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#define LPSS_PCI_MODE_DEFAULT 0x00
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#define LPSS_PCI_MODE_DISABLE 0x01
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#define LPSS_PCI_MODE_ENABLE 0x02
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/* modifiers for various enables */
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uint8_t AzaliaAutoEnable;
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#define AZALIA_FOLLOWS_DEVICETREE 0
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#define AZALIA_FSP_AUTO_ENABLE 1
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uint8_t LpeAcpiModeEnable;
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#define LPE_ACPI_MODE_DISABLED 1
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#define LPE_ACPI_MODE_ENABLED 2
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/* ***** ACPI configuration ***** */
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/* Options for these are in src/arch/x86/include/arch/acpi.h */
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uint8_t fadt_pm_profile;
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uint16_t fadt_boot_arch;
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};
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extern struct chip_operations soc_intel_fsp_baytrail_ops;
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#endif /* _FSP_BAYTRAIL_CHIP_H_ */
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