152 lines
4.4 KiB
C
152 lines
4.4 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <lib.h>
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#include <stdlib.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <device/device.h>
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#include <soc/nvidia/tegra/types.h>
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#include <soc/display.h>
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#include <soc/mipi_dsi.h>
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#include <soc/tegra_dsi.h>
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#include "jdi_25x18_display/panel-jdi-lpm102a188a.h"
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static unsigned long dsi_pads[] = {
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0x060, /* DSIA & DSIB pads */
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0x180, /* DSIC & DSID pads */
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};
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static struct tegra_mipi mipi_data = {
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.regs = (void *)TEGRA_MIPI_CAL_BASE,
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};
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static inline unsigned long tegra_mipi_readl(struct tegra_mipi *mipi,
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unsigned long reg)
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{
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return readl(mipi->regs + (reg << 2));
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}
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static inline void tegra_mipi_writel(struct tegra_mipi *mipi,
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unsigned long value, unsigned long reg)
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{
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writel(value, mipi->regs + (reg << 2));
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}
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static const struct calibration_regs tegra124_mipi_calibration_regs[] = {
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{ .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
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{ .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
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{ .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
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{ .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
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{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
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{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },
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{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },
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};
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static const struct tegra_mipi_config tegra124_mipi_config = {
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.calibrate_clk_lane = 1,
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.regs = tegra124_mipi_calibration_regs,
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.num_pads = ARRAY_SIZE(tegra124_mipi_calibration_regs),
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};
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struct tegra_mipi_device *tegra_mipi_request(struct tegra_mipi_device *device,
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int device_index)
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{
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device->mipi = &mipi_data;
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device->config = &tegra124_mipi_config;
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device->pads = dsi_pads[device_index];
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return device;
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}
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static int tegra_mipi_wait(struct tegra_mipi *mipi)
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{
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u32 poll_interval_us = 1000;
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u32 timeout_us = 250 * 1000;
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unsigned long value;
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do {
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value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
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if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
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(value & MIPI_CAL_STATUS_DONE) != 0)
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return 0;
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if (timeout_us > poll_interval_us)
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timeout_us -= poll_interval_us;
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else
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break;
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udelay(poll_interval_us);
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} while (1);
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printk(BIOS_ERR, "%s: ERROR: timeout\n", __func__);
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return -ETIMEDOUT;
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}
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int tegra_mipi_calibrate(struct tegra_mipi_device *device)
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{
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const struct tegra_mipi_config *cfg = device->config;
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unsigned long value, clk_value;
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unsigned int i;
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int err;
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
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value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
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value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
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tegra_mipi_writel(device->mipi, MIPI_CAL_BIAS_PAD_CFG1_DEFAULT,
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MIPI_CAL_BIAS_PAD_CFG1);
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
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value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
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for (i = 0; i < cfg->num_pads; i++) {
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if (device->pads & BIT(i)) {
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value = MIPI_CAL_CONFIG_SELECT |
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MIPI_CAL_CONFIG_HSPDOS(0) |
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MIPI_CAL_CONFIG_HSPUOS(4) |
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MIPI_CAL_CONFIG_TERMOS(5);
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clk_value = MIPI_CAL_CONFIG_SELECT |
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MIPI_CAL_CONFIG_HSCLKPDOSD(0) |
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MIPI_CAL_CONFIG_HSCLKPUOSD(4);
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} else {
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value = 0;
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clk_value = 0;
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}
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tegra_mipi_writel(device->mipi, value, cfg->regs[i].data);
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if (cfg->calibrate_clk_lane)
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tegra_mipi_writel(device->mipi, clk_value,
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cfg->regs[i].clk);
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}
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value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
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value |= MIPI_CAL_CTRL_START;
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tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
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err = tegra_mipi_wait(device->mipi);
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return err;
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}
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