GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
coreboot-kgpe-d16/util/amdfwtool/data_parse.c

805 lines
23 KiB
C
Raw Normal View History

amdfwtool: Add missing license header Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-03 09:46:53 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
#include <stdio.h>
#include <regex.h>
#include <string.h>
#include <stdlib.h>
util/amdfwtool: portability fixes for FreeBSD Add the stdint.h header, and drop the GLIBC section from amdfwtool.h to build this tool on FreeBSD as well as Linux. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I295fd308b0f5e2902931f02c9455823a614976de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 00:01:59 +01:00
#include <stdint.h>
amdfwtool: Copy string in a safer way The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27 05:11:34 +02:00
#include <assert.h>
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
#include "amdfwtool.h"
/* TODO: a empty line does not matched. */
static const char blank_or_comment_regex[] =
/* a blank line */
"(^[[:space:]]*$)"
"|" /* or ... */
/* a line consisting of: optional whitespace followed by */
"(^[[:space:]]*"
/* a '#' character and optionally, additional characters */
"#.*$)";
static regex_t blank_or_comment_expr;
static const char entries_line_regex[] =
/* optional whitespace */
"^[[:space:]]*"
/* followed by a chunk of nonwhitespace for macro field */
"([^[:space:]]+)"
/* followed by one or more whitespace characters */
"[[:space:]]+"
/* followed by a chunk of nonwhitespace for filename field */
"([^[:space:]]+)"
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
/* followed by an optional whitespace + chunk of nonwhitespace for level field
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
1st char L: Indicator of field "level"
2nd char:
Directory level to be dropped in.
1: Level 1
2: Level 2
b: Level both 1&2
x: use default value hardcoded in table
3rd char:
For A/B recovery. Defined same as 2nd char.
Examples:
L2: Level 2 for normal mode
L12: Level 1 for normal mode, level 2 for A/B mode
Lx1: Use default value for normal mode, level 1 for A/B mode
*/
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
"([[:space:]]+([Ll][12bxBX]{1,2}))?"
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
/* followed by an optional whitespace + chunk of nonwhitespace for hash table field
1st char H: Indicator of field "Hash Table ID"
2nd char:
Table ID to be dropped in.
0: Table 0 / Default Unified Table
1: Table 1
...
9: Table 9
Examples:
H2: Put the hash for the concerned entry in Hash Table 2
*/
"([[:space:]]+([Hh][0-9]+))?"
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
/* followed by optional whitespace */
"[[:space:]]*$";
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
static regex_t entries_line_expr;
enum match_id {
FW_TYPE = 1,
FW_FILE,
OPT_SPACE1,
OPT_LEVEL,
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
OPT_SPACE2,
OPT_HASH_TABLE_ID,
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
N_MATCHES,
};
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
void compile_reg_expr(int cflags, const char *expr, regex_t *reg)
{
static const size_t ERROR_BUF_SIZE = 256;
char error_msg[ERROR_BUF_SIZE];
int result;
result = regcomp(reg, expr, cflags);
if (result != 0) {
regerror(result, reg, error_msg, ERROR_BUF_SIZE);
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "%s\n", error_msg);
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
}
}
amdfwtool: Put soc name setting to fw.cfg from command line The fw.cfg should combine the SOC name. This is for future combo feature. Each entry in combo has its own fw.cfg. The soc_id in struct cb_config can only be available after the fw.cfg is processed. Some functions which take soc_id as a parameter can be simplified. 3/5 (and the key one with same change ID) of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-25 15:58:49 +01:00
static enum platform identify_platform(char *soc_name)
{
if (!strcasecmp(soc_name, "Stoneyridge"))
return PLATFORM_STONEYRIDGE;
else if (!strcasecmp(soc_name, "Carrizo"))
return PLATFORM_CARRIZO;
else if (!strcasecmp(soc_name, "Raven"))
return PLATFORM_RAVEN;
else if (!strcasecmp(soc_name, "Picasso"))
return PLATFORM_PICASSO;
else if (!strcasecmp(soc_name, "Cezanne"))
return PLATFORM_CEZANNE;
else if (!strcasecmp(soc_name, "Mendocino"))
return PLATFORM_MENDOCINO;
else if (!strcasecmp(soc_name, "Renoir"))
return PLATFORM_RENOIR;
else if (!strcasecmp(soc_name, "Lucienne"))
return PLATFORM_LUCIENNE;
else if (!strcasecmp(soc_name, "Phoenix"))
return PLATFORM_PHOENIX;
else if (!strcasecmp(soc_name, "Glinda"))
return PLATFORM_GLINDA;
else
return PLATFORM_UNKNOWN;
}
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
#define SET_LEVEL(tableptr, l, TABLE, ab) \
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
do { \
switch ((l)) { \
case '1': \
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
(tableptr)->level = ab ? TABLE##_LVL1_AB : TABLE##_LVL1; \
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
break; \
case '2': \
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
(tableptr)->level = ab ? TABLE##_LVL2_AB : TABLE##_LVL2; \
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
break; \
case 'b': \
case 'B': \
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
(tableptr)->level = ab ? TABLE##_BOTH_AB : TABLE##_BOTH; \
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
break; \
default: \
/* use default value */ \
break; \
} \
} while (0)
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
extern amd_fw_entry amd_psp_fw_table[];
extern amd_bios_entry amd_bios_table[];
static uint8_t find_register_fw_filename_psp_dir(char *fw_name, char *filename,
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
char level_to_set, uint8_t hash_tbl_id, amd_cb_config *cb_config)
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
{
amd_fw_type fw_type = AMD_FW_INVALID;
amd_fw_entry *psp_tableptr;
uint8_t subprog;
amdfwtool: Add definition of instance for PSP entry Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-16 14:18:40 +02:00
uint8_t instance = 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->have_whitelist) {
amdfwtool:cezanne: use correct bootloader binary for whitelist support PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type 0x73 entry and not type 0x01 (stage1 bootloader). We will also need to change WHL BL filename (Type0x01->Type0x73) in a separate CL. BUG=b:181135622 Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-07 05:15:36 +02:00
fw_type = AMD_FW_PSP_BOOTLOADER_AB;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
} else if (strcmp(fw_name, "PSPBTLDR_AB_STAGE1_FILE") == 0) {
if (cb_config->recovery_ab) {
fw_type = AMD_FW_PSP_BOOTLOADER;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) {
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
if (!cb_config->recovery_ab) {
fw_type = AMD_FW_PSP_BOOTLOADER;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) {
fw_type = AMD_FW_PSP_PUBKEY;
subprog = 0;
} else if (strcmp(fw_name, "PSPRCVR_FILE") == 0) {
fw_type = AMD_FW_PSP_RECOVERY;
subprog = 0;
} else if (strcmp(fw_name, "PUBSIGNEDKEY_FILE") == 0) {
fw_type = AMD_FW_PSP_RTM_PUBKEY;
subprog = 0;
} else if (strcmp(fw_name, "PSPNVRAM_FILE") == 0) {
fw_type = AMD_FW_PSP_NVRAM;
subprog = 0;
} else if (strcmp(fw_name, "SMUSCS_FILE") == 0) {
fw_type = AMD_FW_PSP_SMUSCS;
subprog = 0;
} else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) {
fw_type = AMD_FW_PSP_TRUSTLETS;
subprog = 0;
} else if (strcmp(fw_name, "PSPSECUREDEBUG_FILE") == 0) {
fw_type = AMD_FW_PSP_SECURED_DEBUG;
subprog = 0;
} else if (strcmp(fw_name, "PSP_SMUFW1_SUB0_FILE") == 0) {
fw_type = AMD_FW_PSP_SMU_FIRMWARE;
subprog = 0;
amdfwtool: Add HW IPCFG file whose subprog is 1 And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-07 12:48:11 +01:00
} else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB0") == 0) {
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
fw_type = AMD_HW_IPCFG;
subprog = 0;
amdfwtool: Add HW IPCFG file whose subprog is 1 And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-07 12:48:11 +01:00
} else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB1") == 0) {
fw_type = AMD_HW_IPCFG;
subprog = 1;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) {
fw_type = AMD_FW_PSP_SMU_FIRMWARE;
subprog = 1;
} else if (strcmp(fw_name, "PSP_SMUFW1_SUB2_FILE") == 0) {
fw_type = AMD_FW_PSP_SMU_FIRMWARE;
subprog = 2;
} else if (strcmp(fw_name, "PSP_SMUFW2_SUB0_FILE") == 0) {
fw_type = AMD_FW_PSP_SMU_FIRMWARE2;
subprog = 0;
} else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) {
fw_type = AMD_FW_PSP_SMU_FIRMWARE2;
subprog = 1;
} else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) {
fw_type = AMD_FW_PSP_SMU_FIRMWARE2;
subprog = 2;
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
} else if (strcmp(fw_name, "PSP_BOOT_DRIVER_FILE") == 0) {
fw_type = AMD_BOOT_DRIVER;
subprog = 0;
} else if (strcmp(fw_name, "PSP_SOC_DRIVER_FILE") == 0) {
fw_type = AMD_SOC_DRIVER;
subprog = 0;
} else if (strcmp(fw_name, "PSP_DEBUG_DRIVER_FILE") == 0) {
fw_type = AMD_DEBUG_DRIVER;
subprog = 0;
} else if (strcmp(fw_name, "PSP_INTERFACE_DRIVER_FILE") == 0) {
fw_type = AMD_INTERFACE_DRIVER;
subprog = 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else if (strcmp(fw_name, "PSP_SEC_DBG_KEY_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->unlock_secure) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_FW_PSP_SECURED_DEBUG;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
} else if (strcmp(fw_name, "PSP_SEC_DEBUG_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->unlock_secure) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_DEBUG_UNLOCK;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
} else if (strcmp(fw_name, "PSP_ABL0_FILE") == 0) {
fw_type = AMD_ABL0;
subprog = 0;
} else if (strcmp(fw_name, "PSP_ABL1_FILE") == 0) {
fw_type = AMD_ABL1;
subprog = 0;
} else if (strcmp(fw_name, "PSP_ABL2_FILE") == 0) {
fw_type = AMD_ABL2;
subprog = 0;
} else if (strcmp(fw_name, "PSP_ABL3_FILE") == 0) {
fw_type = AMD_ABL3;
subprog = 0;
} else if (strcmp(fw_name, "PSP_ABL4_FILE") == 0) {
fw_type = AMD_ABL4;
subprog = 0;
} else if (strcmp(fw_name, "PSP_ABL5_FILE") == 0) {
fw_type = AMD_ABL5;
subprog = 0;
} else if (strcmp(fw_name, "PSP_ABL6_FILE") == 0) {
fw_type = AMD_ABL6;
subprog = 0;
} else if (strcmp(fw_name, "PSP_ABL7_FILE") == 0) {
fw_type = AMD_ABL7;
subprog = 0;
} else if (strcmp(fw_name, "PSPSECUREOS_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->use_secureos) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_FW_PSP_SECURED_OS;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
} else if (strcmp(fw_name, "PSPTRUSTLETS_FILE") == 0) {
if (cb_config->use_secureos) {
fw_type = AMD_FW_PSP_TRUSTLETS;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
} else if (strcmp(fw_name, "TRUSTLETKEY_FILE") == 0) {
if (cb_config->use_secureos) {
fw_type = AMD_FW_PSP_TRUSTLETKEY;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
} else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) {
fw_type = AMD_WRAPPED_IKEK;
subprog = 0;
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
} else if (strcmp(fw_name, "PSP_SECG0_FILE") == 0) {
fw_type = AMD_SEC_GASKET;
subprog = 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else if (strcmp(fw_name, "PSP_SECG1_FILE") == 0) {
fw_type = AMD_SEC_GASKET;
subprog = 1;
} else if (strcmp(fw_name, "PSP_SECG2_FILE") == 0) {
fw_type = AMD_SEC_GASKET;
subprog = 2;
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
} else if (strcmp(fw_name, "PSP_MP2FW0_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->load_mp2_fw) {
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
fw_type = AMD_MP2_FW;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else if (strcmp(fw_name, "PSP_MP2FW1_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->load_mp2_fw) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_MP2_FW;
subprog = 1;
} else {
fw_type = AMD_FW_SKIP;
}
} else if (strcmp(fw_name, "PSP_MP2FW2_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->load_mp2_fw) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_MP2_FW;
subprog = 2;
} else {
fw_type = AMD_FW_SKIP;
}
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
} else if (strcmp(fw_name, "PSP_C20MP_FILE") == 0) {
fw_type = AMD_FW_C20_MP;
subprog = 0;
} else if (strcmp(fw_name, "AMF_SRAM_FILE") == 0) {
fw_type = AMD_FW_AMF_SRAM;
subprog = 0;
} else if (strcmp(fw_name, "AMF_DRAM_FILE_INS0") == 0) {
fw_type = AMD_FW_AMF_DRAM;
subprog = 0;
instance = 0;
} else if (strcmp(fw_name, "AMF_DRAM_FILE_INS1") == 0) {
fw_type = AMD_FW_AMF_DRAM;
subprog = 0;
instance = 1;
} else if (strcmp(fw_name, "AMF_WLAN_FILE_INS0") == 0) {
fw_type = AMD_FW_AMF_WLAN;
subprog = 0;
instance = 0;
} else if (strcmp(fw_name, "AMF_WLAN_FILE_INS1") == 0) {
fw_type = AMD_FW_AMF_WLAN;
subprog = 0;
instance = 1;
} else if (strcmp(fw_name, "AMF_MFD_FILE") == 0) {
fw_type = AMD_FW_AMF_MFD;
subprog = 0;
} else if (strcmp(fw_name, "MPCCX_FILE") == 0) {
fw_type = AMD_FW_MPCCX;
subprog = 0;
} else if (strcmp(fw_name, "LSDMA_FILE") == 0) {
fw_type = AMD_FW_LSDMA;
subprog = 0;
} else if (strcmp(fw_name, "MINIMSMU_FILE") == 0) {
fw_type = AMD_FW_MINIMSMU;
instance = 0;
subprog = 0;
} else if (strcmp(fw_name, "MINIMSMU_FILE_INS1") == 0) {
fw_type = AMD_FW_MINIMSMU;
instance = 1;
subprog = 0;
} else if (strcmp(fw_name, "SRAM_FW_EXT_FILE") == 0) {
fw_type = AMD_FW_SRAM_FW_EXT;
subprog = 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) {
fw_type = AMD_DRIVER_ENTRIES;
subprog = 0;
} else if (strcmp(fw_name, "PSP_S0I3_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->s0i3) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_S0I3_DRIVER;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
} else if (strcmp(fw_name, "AMD_DRIVER_ENTRIES") == 0) {
fw_type = AMD_DRIVER_ENTRIES;
subprog = 0;
} else if (strcmp(fw_name, "VBIOS_BTLOADER_FILE") == 0) {
fw_type = AMD_VBIOS_BTLOADER;
subprog = 0;
} else if (strcmp(fw_name, "SECURE_POLICY_L1_FILE") == 0) {
fw_type = AMD_FW_TOS_SEC_POLICY;
subprog = 0;
} else if (strcmp(fw_name, "UNIFIEDUSB_FILE") == 0) {
fw_type = AMD_FW_USB_PHY;
subprog = 0;
} else if (strcmp(fw_name, "DRTMTA_FILE") == 0) {
fw_type = AMD_FW_DRTM_TA;
subprog = 0;
} else if (strcmp(fw_name, "KEYDBBL_FILE") == 0) {
fw_type = AMD_FW_KEYDB_BL;
subprog = 0;
} else if (strcmp(fw_name, "KEYDB_TOS_FILE") == 0) {
fw_type = AMD_FW_KEYDB_TOS;
subprog = 0;
amdfwtool: Add SPL support SPL: Security Patch Level The data in SPL is used for FW anti-rollback, preventing rollback of platform level firmware to older version that are deemed vulnerable from a security point of view. BUG=b:216096562 Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-27 15:38:27 +01:00
} else if (strcmp(fw_name, "SPL_TABLE_FILE") == 0) {
amdfwtool: Add options to support mainboard specific SPL table For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 04:51:26 +01:00
if (cb_config->have_mb_spl) {
util/amdfwtool/data_parse: fix SPL table handling regression Use the SPL table binary from the config file if no override is specified via the spl-table command line argument. This fixes a regression caused by commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-02 03:49:07 +02:00
fw_type = AMD_FW_SKIP;
} else {
amdfwtool: Add options to support mainboard specific SPL table For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 04:51:26 +01:00
fw_type = AMD_FW_SPL;
subprog = 0;
}
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
} else if (strcmp(fw_name, "DMCUERAMDCN21_FILE") == 0) {
fw_type = AMD_FW_DMCU_ERAM;
subprog = 0;
} else if (strcmp(fw_name, "DMCUINTVECTORSDCN21_FILE") == 0) {
fw_type = AMD_FW_DMCU_ISR;
subprog = 0;
util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-24 02:04:51 +01:00
} else if (strcmp(fw_name, "MSMU_FILE") == 0) {
fw_type = AMD_FW_MSMU;
subprog = 0;
} else if (strcmp(fw_name, "DMCUB_FILE") == 0) {
fw_type = AMD_FW_DMCUB;
subprog = 0;
} else if (strcmp(fw_name, "SPIROM_CONFIG_FILE") == 0) {
fw_type = AMD_FW_SPIROM_CFG;
subprog = 0;
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
} else if (strcmp(fw_name, "MPIO_FILE") == 0) {
fw_type = AMD_FW_MPIO;
subprog = 0;
} else if (strcmp(fw_name, "TPMLITE_FILE") == 0) {
fw_type = AMD_FW_TPMLITE;
subprog = 0;
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
} else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) {
fw_type = AMD_FW_KVM_IMAGE;
subprog = 0;
} else if (strcmp(fw_name, "RPMC_FILE") == 0) {
fw_type = AMD_RPMC_NVRAM;
subprog = 0;
amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-02 11:48:23 +01:00
} else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) {
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
if (!cb_config->have_whitelist || cb_config->recovery_ab) {
amdfwtool:cezanne: use correct bootloader binary for whitelist support PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type 0x73 entry and not type 0x01 (stage1 bootloader). We will also need to change WHL BL filename (Type0x01->Type0x73) in a separate CL. BUG=b:181135622 Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-07 05:15:36 +02:00
fw_type = AMD_FW_PSP_BOOTLOADER_AB;
subprog = 0;
} else {
fw_type = AMD_FW_SKIP;
}
util/amdfwtool: Add IKEK key for Trusted Application This binary file is required for use by Trusted Applications that execute in PSP. BUG=b:229947314 TEST=Build and boot to OS in Skyrim. Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-04 02:16:34 +02:00
} else if (strcmp(fw_name, "TA_IKEK_FILE") == 0) {
fw_type = AMD_TA_IKEK;
subprog = 0;
util/amdfwtool: Add UMSMU blob support Add PSP blob Type 0xA2 uMsmu support. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib38ec03bf20f46774f7438b21d18704cc1ec57fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-07 18:12:40 +01:00
} else if (strcmp(fw_name, "UMSMU_FILE") == 0) {
fw_type = AMD_FW_UMSMU;
subprog = 0;
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
} else if (strcmp(fw_name, "PSP_OEM_ABL_KEY_FILE") == 0) {
fw_type = AMD_FW_ABL_PUBKEY;
subprog = 0;
} else if (strcmp(fw_name, "PSP_MP5FW_SUB0_FILE") == 0) {
fw_type = AMD_FW_MP5;
subprog = 0;
} else if (strcmp(fw_name, "PSP_MP5FW_SUB1_FILE") == 0) {
fw_type = AMD_FW_MP5;
subprog = 1;
} else if (strcmp(fw_name, "PSP_MP5FW_SUB2_FILE") == 0) {
fw_type = AMD_FW_MP5;
subprog = 2;
} else if (strcmp(fw_name, "PSP_DXIOFW_FILE") == 0) {
fw_type = AMD_FW_DXIO;
subprog = 0;
} else if (strcmp(fw_name, "PSP_MPIOFW_FILE") == 0) {
fw_type = AMD_FW_MPIO;
subprog = 0;
amdfwtool: Add entry RIB whose subprog equals 1 For the PHX, it uses subprog 0. For the PHX2, it uses subprog 1. Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-30 06:52:30 +01:00
} else if (strcmp(fw_name, "PSP_RIB_FILE_SUB0") == 0) {
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
fw_type = AMD_RIB;
subprog = 0;
amdfwtool: Add entry RIB whose subprog equals 1 For the PHX, it uses subprog 0. For the PHX2, it uses subprog 1. Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-30 06:52:30 +01:00
} else if (strcmp(fw_name, "PSP_RIB_FILE_SUB1") == 0) {
fw_type = AMD_RIB;
subprog = 1;
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
} else if (strcmp(fw_name, "FEATURE_TABLE_FILE") == 0) {
fw_type = AMD_FW_FCFG_TABLE;
subprog = 0;
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
} else if (strcmp(fw_name, "PSP_MPDMATFFW_FILE") == 0) {
fw_type = AMD_FW_MPDMA_TF;
subprog = 0;
} else if (strcmp(fw_name, "PSP_GMI3PHYFW_FILE") == 0) {
fw_type = AMD_FW_GMI3_PHY;
subprog = 0;
} else if (strcmp(fw_name, "PSP_MPDMAPMFW_FILE") == 0) {
fw_type = AMD_FW_MPDMA_PM;
subprog = 0;
} else if (strcmp(fw_name, "PSP_TOKEN_UNLOCK_FILE") == 0) {
fw_type = AMD_TOKEN_UNLOCK;
subprog = 0;
} else if (strcmp(fw_name, "SEV_DATA_FILE") == 0) {
fw_type = AMD_SEV_DATA;
subprog = 0;
} else if (strcmp(fw_name, "SEV_CODE_FILE") == 0) {
fw_type = AMD_SEV_CODE;
subprog = 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else {
fw_type = AMD_FW_INVALID;
/* TODO: Add more */
}
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
/* Search and fill the filename */
psp_tableptr = &amd_psp_fw_table[0];
if (fw_type != AMD_FW_SKIP && fw_type != AMD_FW_INVALID) {
while (psp_tableptr->type != AMD_FW_INVALID) {
/* instance are not used in PSP table */
amdfwtool: Add definition of instance for PSP entry Change-Id: I9f6250fd0e26cfae2cc2128ca9413a5621d2df0c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-16 14:18:40 +02:00
if (psp_tableptr->type == fw_type && psp_tableptr->subprog == subprog
&& psp_tableptr->inst == instance) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
psp_tableptr->filename = filename;
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
SET_LEVEL(psp_tableptr, level_to_set, PSP,
cb_config->recovery_ab);
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
psp_tableptr->hash_tbl_id = hash_tbl_id;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
break;
}
psp_tableptr++;
}
}
if (fw_type == AMD_FW_INVALID)
return 0;
else
return 1;
}
soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17 10:48:27 +01:00
#define PMUI_STR_BASE "PSP_PMUI_FILE"
#define PMUD_STR_BASE "PSP_PMUD_FILE"
#define PMU_STR_BASE_LEN strlen(PMUI_STR_BASE)
#define PMU_STR_SUB_INDEX strlen(PMUI_STR_BASE"_SUB")
#define PMU_STR_INS_INDEX strlen(PMUI_STR_BASE"_SUBx_INS")
amdfwtool: Check the real length of PMU string The length should be checked before the PMU_STR_INS_INDEX(th) character is accessed, otherwise it is going to an access violation. Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 02:47:59 +01:00
#define PMU_STR_ALL_LEN strlen(PMUI_STR_BASE"_SUBx_INSx")
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename,
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
char level_to_set, amd_cb_config *cb_config)
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
{
amd_bios_type fw_type = AMD_BIOS_INVALID;
amd_bios_entry *bhd_tableptr;
util/amdfwtool: add missing zero-initialization for local variable Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20 20:08:42 +01:00
uint8_t subprog = 0;
uint8_t instance = 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
(void) (cb_config); /* Remove warning and reserved for future. */
soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17 10:48:27 +01:00
if (strncmp(fw_name, PMUI_STR_BASE, PMU_STR_BASE_LEN) == 0) {
amdfwtool: Check the real length of PMU string The length should be checked before the PMU_STR_INS_INDEX(th) character is accessed, otherwise it is going to an access violation. Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 02:47:59 +01:00
assert(strlen(fw_name) == PMU_STR_ALL_LEN);
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_BIOS_PMUI;
util/amdfwtool/data_parse: fix PMU subprogram/instance ID handling The parsing of the PMU binary subprogram and instance numbers only worked correctly for the cases where the ID in the name in the fw.cfg file was between 0 and 9, but returned wrong results if it was between a and f. Switch to using strtol with a base of 16 instead of subtracting the char '0' from the char in the filename in find_register_fw_filename_bios_dir to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-28 18:00:39 +02:00
subprog = strtol(&fw_name[PMU_STR_SUB_INDEX], NULL, 16);
instance = strtol(&fw_name[PMU_STR_INS_INDEX], NULL, 16);
soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17 10:48:27 +01:00
} else if (strncmp(fw_name, PMUD_STR_BASE, PMU_STR_BASE_LEN) == 0) {
amdfwtool: Check the real length of PMU string The length should be checked before the PMU_STR_INS_INDEX(th) character is accessed, otherwise it is going to an access violation. Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 02:47:59 +01:00
assert(strlen(fw_name) == PMU_STR_ALL_LEN);
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
fw_type = AMD_BIOS_PMUD;
util/amdfwtool/data_parse: fix PMU subprogram/instance ID handling The parsing of the PMU binary subprogram and instance numbers only worked correctly for the cases where the ID in the name in the fw.cfg file was between 0 and 9, but returned wrong results if it was between a and f. Switch to using strtol with a base of 16 instead of subtracting the char '0' from the char in the filename in find_register_fw_filename_bios_dir to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-28 18:00:39 +02:00
subprog = strtol(&fw_name[PMU_STR_SUB_INDEX], NULL, 16);
instance = strtol(&fw_name[PMU_STR_INS_INDEX], NULL, 16);
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
} else if (strcmp(fw_name, "RTM_PUBKEY_FILE") == 0) {
fw_type = AMD_BIOS_RTM_PUBKEY;
subprog = 0;
instance = 0;
amdfwtool: Move the MP2CFG checking to category of BIOS data Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-14 14:54:06 +01:00
} else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) {
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (cb_config->load_mp2_fw) {
amdfwtool: Move the MP2CFG checking to category of BIOS data Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-14 14:54:06 +01:00
fw_type = AMD_BIOS_MP2_CFG;
subprog = 0;
} else {
util/amdfwtool: Fix all warnings Fixes these warnings: warning: alignment 1 of 'struct _psp_directory_table' is less than 16 [-Wpacked-not-aligned] warning: alignment 1 of 'struct _psp_combo_directory' is less than 16 [-Wpacked-not-aligned] In function 'find_register_fw_filename_bios_dir': warning: implicit conversion from 'enum _amd_fw_type' to 'amd_bios_type' {aka 'enum _amd_bios_type'} [-Wenum-conversion] BUG=None TEST=Build and verify binaries are identical. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I761d9893ac6737b42af96c4b2a57c5a4fc61ab05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-14 05:42:46 +01:00
fw_type = AMD_BIOS_SKIP;
amdfwtool: Move the MP2CFG checking to category of BIOS data Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-14 14:54:06 +01:00
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
} else {
fw_type = AMD_BIOS_INVALID;
}
bhd_tableptr = amd_bios_table;
if (fw_type != AMD_BIOS_INVALID && fw_type != AMD_BIOS_SKIP) {
while (bhd_tableptr->type != AMD_BIOS_INVALID) {
if (bhd_tableptr->type == fw_type &&
bhd_tableptr->subpr == subprog &&
bhd_tableptr->inst == instance) {
bhd_tableptr->filename = filename;
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
SET_LEVEL(bhd_tableptr, level_to_set, BDT,
cb_config->recovery_ab);
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
break;
}
bhd_tableptr++;
}
}
if (fw_type == AMD_BIOS_INVALID)
return 0;
else
return 1;
}
#define MAX_LINE_SIZE 1024
int get_input_file_line(FILE *f, char line[], int line_buf_size)
{
if (fgets(line, line_buf_size, f) == NULL)
return LINE_EOF;
/* If the file contains a line that is too long, then it's best
* to let the user know right away rather than passing back a
* truncated result that will lead to problems later on.
*/
line[strlen(line) - 1] = '\0';
if (strlen(line) == ((size_t) (line_buf_size - 1))) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "The line size in config file should be lower than %d bytes.\n",
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
MAX_LINE_SIZE);
exit(1);
}
return OK;
}
amdfwtool: Clear struct match before regular expression matching If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 10:18:00 +01:00
static int is_valid_entry(char *oneline, regmatch_t match[N_MATCHES])
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
{
amdfwtool: Clear struct match before regular expression matching If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 10:18:00 +01:00
int retval, index;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
amdfwtool: Clear struct match before regular expression matching If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 10:18:00 +01:00
for (index = 0; index < N_MATCHES; index++) {
match[index].rm_so = -1;
match[index].rm_eo = -1;
}
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
if (regexec(&entries_line_expr, oneline, N_MATCHES, match, 0) == 0) {
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
/* match[1]: FW type
match[2]: FW filename
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
match[4]: Optional directory level to be dropped
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
match[6]: Optional hash table ID to put the hash for the entry
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
*/
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
oneline[match[FW_TYPE].rm_eo] = '\0';
oneline[match[FW_FILE].rm_eo] = '\0';
oneline[match[OPT_LEVEL].rm_eo] = '\0';
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
oneline[match[OPT_HASH_TABLE_ID].rm_eo] = '\0';
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
retval = 1;
} else {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
retval = 0;
amdfwtool: Add an optional column of level The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 12:00:09 +02:00
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
return retval;
}
static int skip_comment_blank_line(char *oneline)
{
int retval;
if (regexec(&blank_or_comment_expr, oneline, 0, NULL, 0) == 0) {
/* skip comment and blank */
retval = 1;
} else {
/* no match */
retval = 0;
}
return retval;
}
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
static char get_level_from_config(char *line, regoff_t level_index, amd_cb_config *cb_config)
amdfwtool: Check the length of matching string before accessing If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character is got or access violation happens. Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-01 10:22:52 +01:00
{
char lvl = 'x';
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
/* If the optional level field is present, extract the level char. */
amdfwtool: Check the length of matching string before accessing If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character is got or access violation happens. Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-01 10:22:52 +01:00
if (level_index != -1) {
if (cb_config->recovery_ab == 0)
lvl = line[level_index + 1];
else if (strlen(&line[level_index]) >= 3)
lvl = line[level_index + 2];
}
assert(lvl == 'x' || lvl == 'X' ||
lvl == 'b' || lvl == 'B' ||
lvl == '1' || lvl == '2');
return lvl;
}
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
static uint8_t get_hash_tbl_id(char *line, regoff_t hash_tbl_index)
{
uint8_t tbl = 0;
/* If the optional hash table field is present, extract the table id char. */
if (hash_tbl_index != -1)
tbl = (uint8_t)atoi(&line[hash_tbl_index + 1]);
assert(tbl < MAX_NUM_HASH_TABLES);
return tbl;
}
amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-03-27 11:15:35 +01:00
static uint8_t process_one_line(char *oneline, regmatch_t *match, char *dir,
amdfwtool: Remove the option --list which nobody uses It was used for printing the dependencies which is now taken by macro DEP_FILES in soc/amd/common/Makefile.inc. TEST=binary identical test on google/guybrush amd/chausie Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09 04:43:55 +01:00
amd_cb_config *cb_config)
amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-03-27 11:15:35 +01:00
{
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
char *path_filename, *fn = &(oneline[match[FW_FILE].rm_so]);
char *fw_type_str = &(oneline[match[FW_TYPE].rm_so]);
regoff_t ch_lvl_index = match[OPT_LEVEL].rm_so == match[OPT_LEVEL].rm_eo ?
-1 : match[OPT_LEVEL].rm_so;
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
regoff_t ch_hash_tbl_index =
match[OPT_HASH_TABLE_ID].rm_so == match[OPT_HASH_TABLE_ID].rm_eo ?
-1 : match[OPT_HASH_TABLE_ID].rm_so;
char ch_lvl = get_level_from_config(oneline, ch_lvl_index, cb_config);
uint8_t ch_hash_tbl = get_hash_tbl_id(oneline, ch_hash_tbl_index);
amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-03-27 11:15:35 +01:00
path_filename = malloc(MAX_LINE_SIZE * 2 + 2);
util/amdfwtool: Update config parser to accept full paths This allows individual components to be placed in a location other than what is specified by the FIRMWARE_LOCATION line. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3a83e52d081a5909d54eacc575dd2b40b09e4038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-03-08 22:58:51 +01:00
if (strchr(fn, '/'))
snprintf(path_filename, MAX_LINE_SIZE * 2 + 2, "%.*s",
MAX_LINE_SIZE, fn);
else
snprintf(path_filename, MAX_LINE_SIZE * 2 + 2, "%.*s/%.*s",
MAX_LINE_SIZE, dir, MAX_LINE_SIZE, fn);
amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-03-27 11:15:35 +01:00
if (find_register_fw_filename_psp_dir(
util/amdfwtool: Add ability to split hash table Hash table containing hashes of all signed PSP binaries is compiled at build time and installed into the concerned CBFS. During boot, PSP verstage reads the hash table binary and passes it to PSP bootloader. PSP bootloader in turn uses the hash table to verify the signed PSP binaries. Currently the hashes for all the signed PSP binaries are compiled into one hash table. On upcoming platforms with more number of signed PSP binaries, PSP bootloader does not have resources to handle one monolithic hash table. Instead PSP bootloader recommends splitting them into smaller hash tables (currently limited to 3 hash tables). Update amdfwtool tool to support splitting hash tables. This is done by adding an optional hash table id to the entries in the amdfw.cfg file. By default, one hash table binary is always compiled and it's name is of the format ${signed_rom}.hash. If an entry has a hash table id defined, then this utility will compile a separate hash table binary whose name is of the format ${signed_rom}.${N}.hash where N is the hash table id. BUG=b:277292697 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table is identical with and without this change. Perform suspend/resume cycles, warm/cold reset cycles for 50 iterations each. TEST=Artificially inject hash table id against some entries in amdfw.cfg and ensure that the concerned hash table binaries are getting compiled. Change-Id: I7ef338d67695a34c33b5c166924832939f381191 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 21:34:41 +02:00
fw_type_str, path_filename, ch_lvl, ch_hash_tbl, cb_config) == 0) {
amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-03-27 11:15:35 +01:00
if (find_register_fw_filename_bios_dir(
fw_type_str, path_filename, ch_lvl, cb_config) == 0) {
fprintf(stderr, "Module's name \"%s\" is not valid\n", fw_type_str);
return 0; /* Stop parsing. */
}
}
return 1;
}
amdfwtool: Put soc name setting to fw.cfg from command line The fw.cfg should combine the SOC name. This is for future combo feature. Each entry in combo has its own fw.cfg. The soc_id in struct cb_config can only be available after the fw.cfg is processed. Some functions which take soc_id as a parameter can be simplified. 3/5 (and the key one with same change ID) of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-25 15:58:49 +01:00
static bool needs_ish(enum platform platform_type)
{
if (platform_type == PLATFORM_MENDOCINO || platform_type == PLATFORM_PHOENIX || platform_type == PLATFORM_GLINDA)
return true;
else
return false;
}
static bool is_second_gen(enum platform platform_type)
{
switch (platform_type) {
case PLATFORM_CARRIZO:
case PLATFORM_STONEYRIDGE:
case PLATFORM_RAVEN:
case PLATFORM_PICASSO:
return false;
case PLATFORM_RENOIR:
case PLATFORM_LUCIENNE:
case PLATFORM_CEZANNE:
case PLATFORM_MENDOCINO:
case PLATFORM_PHOENIX:
case PLATFORM_GLINDA:
return true;
case PLATFORM_UNKNOWN:
default:
fprintf(stderr, "Error: Invalid SOC name.\n\n");
return false;
}
}
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
#define FW_LOCATION "FIRMWARE_LOCATION"
#define SOC_NAME "SOC_NAME"
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
/*
return value:
0: The config file can not be parsed correctly.
1: The config file can be parsed correctly.
*/
amdfwtool: Remove the option --list which nobody uses It was used for printing the dependencies which is now taken by macro DEP_FILES in soc/amd/common/Makefile.inc. TEST=binary identical test on google/guybrush amd/chausie Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09 04:43:55 +01:00
uint8_t process_config(FILE *config, amd_cb_config *cb_config)
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
{
amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-03-27 11:15:35 +01:00
char oneline[MAX_LINE_SIZE];
amdfwtool: Clear struct match before regular expression matching If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 10:18:00 +01:00
regmatch_t match[N_MATCHES];
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
char dir[MAX_LINE_SIZE] = {'\0'};
amdfwtool: Copy string in a safer way The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27 05:11:34 +02:00
uint32_t dir_len;
amdfwtool: Clear struct match before regular expression matching If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 10:18:00 +01:00
int index;
for (index = 0; index < N_MATCHES; index++) {
match[index].rm_so = -1;
match[index].rm_eo = -1;
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
compile_reg_expr(REG_EXTENDED | REG_NEWLINE,
blank_or_comment_regex, &blank_or_comment_expr);
compile_reg_expr(REG_EXTENDED | REG_NEWLINE,
entries_line_regex, &entries_line_expr);
/* Get a line */
soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06 06:03:11 +02:00
/* Get FIRMWARE_LOCATION in the first loop */
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) {
/* get a line */
if (skip_comment_blank_line(oneline))
continue;
if (is_valid_entry(oneline, match)) {
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
if (strcmp(&(oneline[match[FW_TYPE].rm_so]), FW_LOCATION) == 0) {
dir_len = match[FW_FILE].rm_eo - match[FW_FILE].rm_so;
amdfwtool: Copy string in a safer way The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27 05:11:34 +02:00
assert(dir_len < MAX_LINE_SIZE);
snprintf(dir, MAX_LINE_SIZE, "%.*s", dir_len,
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
&(oneline[match[FW_FILE].rm_so]));
} else if (strcmp(&(oneline[match[FW_TYPE].rm_so]), SOC_NAME) == 0) {
cb_config->soc_id = identify_platform(
&(oneline[match[FW_FILE].rm_so]));
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
}
}
}
amdfwtool: Put soc name setting to fw.cfg from command line The fw.cfg should combine the SOC name. This is for future combo feature. Each entry in combo has its own fw.cfg. The soc_id in struct cb_config can only be available after the fw.cfg is processed. Some functions which take soc_id as a parameter can be simplified. 3/5 (and the key one with same change ID) of split changes of https://review.coreboot.org/c/coreboot/+/58552/28 Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-25 15:58:49 +01:00
cb_config->second_gen = is_second_gen(cb_config->soc_id);
if (needs_ish(cb_config->soc_id))
cb_config->need_ish = true;
if (cb_config->need_ish)
cb_config->recovery_ab = true;
if (cb_config->recovery_ab)
cb_config->multi_level = true;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
if (dir[0] == '\0') {
fprintf(stderr, "No line with FIRMWARE_LOCATION\n");
return 0;
}
fseek(config, 0, SEEK_SET);
/* Get a line */
while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) {
/* get a line */
if (skip_comment_blank_line(oneline))
continue;
if (is_valid_entry(oneline, match)) {
util/amdfwtool: Consolidate entry line regex pattern There are 2 regex patterns defined to process the lines from *fw.cfg: 1) for lines with mandatory entries 2) for lines with mandatory + optional entries Consolidate the regex pattern. Add enums for matching regex caller groups so that the human readable group IDs can be used instead of magic numbers. BUG=None TEST=Build Skyrim BIOS which only have mandatory entries. Build Guybrush BIOS image which have both mandatory and optional entries. Confirm that the amdfw.rom built before and after this change have matching SHA in both Skyrim and Guybrush images. This ensures that the optional level entries in Guybrush are handled as expected. Boot to OS in Skyrim. Change-Id: I7289ddbbec4d5daefe64f59b687ba3a4af46d052 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-05-03 06:10:57 +02:00
if (strcmp(&(oneline[match[FW_TYPE].rm_so]), FW_LOCATION) == 0 ||
strcmp(&(oneline[match[FW_TYPE].rm_so]), SOC_NAME) == 0) {
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
continue;
} else {
amdfwtool: Remove the option --list which nobody uses It was used for printing the dependencies which is now taken by macro DEP_FILES in soc/amd/common/Makefile.inc. TEST=binary identical test on google/guybrush amd/chausie Change-Id: I1b86df2cb2ed178cf0a263c50ccb3e2254a3852b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73627 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09 04:43:55 +01:00
if (process_one_line(oneline, match, dir,
amdfwtool: Add a function to make the calling stack less deep And make less levels of indentations in the code. Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-03-27 11:15:35 +01:00
cb_config) == 0)
return 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
}
} else {
fprintf(stderr, "AMDFWTOOL config file line can't be parsed \"%s\"\n", oneline);
return 0;
}
}
return 1;
}