46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define SPI_FPR_SHIFT 12
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#define SPI_FPR_MASK 0x7fff
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#define SPI_FPR_BASE_SHIFT 0
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#define SPI_FPR_LIMIT_SHIFT 16
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#define SPI_FPR_RPE (1 << 15) /* Read Protect */
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#define SPI_FPR_WPE (1 << 31) /* Write Protect */
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#define SPI_FPR(base, limit) \
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(((((limit) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_LIMIT_SHIFT) |\
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((((base) >> SPI_FPR_SHIFT) & SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT))
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struct fpr_info {
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/* Offset of first FPR register */
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uintptr_t base;
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/* Maximum number of FPR registers */
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uint8_t max;
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};
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/*
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* SoC is expected to implement this function to provide address of first FPR
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* register and max count of FPR registers.
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*
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* On success return 0 else -1.
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*/
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int spi_get_fpr_info(struct fpr_info *info);
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/*
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* Protect range of SPI flash defined by [start, start+size-1] using Flash
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* Protected Range (FPR) register if available.
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*/
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int spi_flash_protect(u32 start, u32 size);
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