2012-04-04 00:07:22 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <watchdog.h>
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//
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// Disable PCH Watchdog timer at SB_RCBA+0x3410
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//
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// Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
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//
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void watchdog_off(void)
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{
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2018-05-25 08:29:27 +02:00
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struct device *dev;
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2012-04-04 00:07:22 +02:00
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unsigned long value, base;
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/* Turn off the ICH7 watchdog. */
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dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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/* Enable I/O space. */
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value = pci_read_config16(dev, 0x04);
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value |= (1 << 10);
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pci_write_config16(dev, 0x04, value);
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/* Get TCO base. */
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base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
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/* Disable the watchdog timer. */
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value = inw(base + 0x08);
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value |= 1 << 11;
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outw(value, base + 0x08);
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/* Clear TCO timeout status. */
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outw(0x0008, base + 0x04);
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outw(0x0002, base + 0x06);
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printk(BIOS_DEBUG, "PCH watchdog disabled\n");
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}
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