91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include "southbridge/intel/i82801gx/nvs.h"
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#include "southbridge/intel/i82801gx/i82801gx.h"
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#include <pc80/mc146818rtc.h>
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#include <delay.h>
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/* The southbridge SMI handler checks whether gnvs has a
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* valid pointer before calling the trap handler
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*/
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extern global_nvs_t *gnvs;
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static void mainboard_smm_init(void)
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{
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printk(BIOS_DEBUG, "initializing SMI\n");
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}
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int mainboard_io_trap_handler(int smif)
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{
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static int smm_initialized;
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if (!smm_initialized) {
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mainboard_smm_init();
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smm_initialized = 1;
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}
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switch (smif) {
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default:
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return 0;
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}
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/* On success, the IO Trap Handler returns 1
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* On failure, the IO Trap Handler returns a value != 1 */
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return 1;
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}
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int mainboard_smi_apmc(u8 data)
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{
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u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
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u8 tmp;
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printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
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if (!pmbase)
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return 0;
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switch(data) {
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case APM_CNT_ACPI_ENABLE:
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/* route H8SCI to SCI */
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outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
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tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
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tmp &= ~0x03;
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tmp |= 0x02;
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
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break;
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case APM_CNT_ACPI_DISABLE:
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/* route H8SCI# to SMI */
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outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
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tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
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tmp &= ~0x03;
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tmp |= 0x01;
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
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break;
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default:
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break;
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}
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return 0;
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}
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