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coreboot-kgpe-d16/spd/ddr4/set-0/parts_spd_manifest.generate...

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spd: Generate SPDs under spd/ using unified spd_gen tool Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 05:08:19 +02:00
# Generated by:
mb/google/volteer/eldrid: Add new DDR4 part H5AG36EXNDX019 Hynix H5AG36EXNDX019 is used by the volteer variant Eldrid. Add it to the DDR4 parts list and regenerate the SPDs using spd_gen. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I3383dfa4e87571d920144d204270cdf646a19abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-13 09:50:25 +02:00
# ../../util/spd_tools/bin/spd_gen memory_parts.json ddr4
spd: Generate SPDs under spd/ using unified spd_gen tool Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 05:08:19 +02:00
H5AN8G6NDJR-XNC,spd-1.hex
MT40A512M16TB-062E:J,spd-1.hex
H5ANAG6NCMR-XNC,spd-2.hex
HMA851S6CJR6N-VK,spd-3.hex
K4A8G165WC-BCTD,spd-3.hex
H5AN8G6NCJR-VKC,spd-3.hex
MT40A1G16KNR-075:E,spd-4.hex
K4AAG165WB-MCTD,spd-5.hex
H5ANAG6NCMR-VKC,spd-6.hex
K4A8G165WC-BCWE,spd-1.hex
MT40A1G16KD-062E:E,spd-7.hex
K4AAG165WA-BCWE,spd-7.hex
H5AN8G6NCJR-XNC,spd-1.hex
K4AAG165WA-BCTD,spd-8.hex
H5ANAG6NDMR-XNC,spd-2.hex
H5ANAG6NCJR-XNC,spd-9.hex
mb/google/volteer/eldrid: Add new DDR4 part H5AG36EXNDX019 Hynix H5AG36EXNDX019 is used by the volteer variant Eldrid. Add it to the DDR4 parts list and regenerate the SPDs using spd_gen. BUG=b:236739240 BRANCH=Volteer TEST="util/spd_tools/bin/spd_gen memory_parts.json ddr4" and verify it builds successfully. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I3383dfa4e87571d920144d204270cdf646a19abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-13 09:50:25 +02:00
H5AG36EXNDX019,spd-1.hex
spd: Generate SPDs under spd/ using unified spd_gen tool Use the new unified version of the spd_gen tool to generate all LP4x and DDR4 SPDs, storing them in a new spd/ directory. Storing them in a common location allows platforms with the same SPD requirements to share SPD files, reducing duplication compared to storing SPDs in soc/ and mainboard/ directories. For each memory technology there are multiple sets of SPDs. Each set corresponds to a set of platforms with different SPD requirements, e.g. due to different memory training code expectations. A manifest file (platforms_manifest.generated.txt) lists the platform -> set mappings. Commands used to generate SPDs: cp util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt \ spd/lp4x/memory_parts.json cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Iac82847a1a0c1f2e7271d0d3b3a7261849813a24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 05:08:19 +02:00
K4AAG165WB-BCWE,spd-9.hex
MT40A1G16RC-062E:B,spd-9.hex
MT40A512M16TB-062E:R,spd-1.hex
spd: Add SPD for 4JQA-0622AD to spd/ Since generating the SPDs under spd/, a new part was added in https://review.coreboot.org/57550. Regenerate the SPDs to include this new part. Commands used: cp util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt \ spd/ddr4/memory_parts.json util/spd_tools/bin/spd_gen spd/ddr4/memory_parts.json ddr4 BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ie673d1a386479f690182050ce4fee7d252ec9530 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22 01:27:48 +02:00
4JQA-0622AD,spd-1.hex