coreboot-kgpe-d16/targets/embeddedplanet/ep405pc/Config.lb

# Config file for Embedded Planet EP405PC board
# This will make a target directory of ./ep405pc

loadoptions

target ep405pc

uses CPU_OPT
uses CROSS_COMPILE 
uses HAVE_OPTION_TABLE
uses CONFIG_COMPRESS 
uses CONFIG_CHIP_CONFIGURE
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses CONFIG_CONSOLE_SERIAL8250 
uses TTYS0_BASE UART0_IO_BASE 
uses NO_POST
uses CONFIG_IDE_STREAM 
uses CONFIG_SYS_CLK_FREQ
uses IDE_BOOT_DRIVE
uses IDE_SWAB IDE_OFFSET 
uses ROM_SIZE
uses _RESET
uses _EXCEPTION_VECTORS
uses _ROMBASE
uses _ROMSTART
uses _RAMBASE
uses _RAMSTART
uses EMBEDDED_RAM_SIZE
uses STACK_SIZE HEAP_SIZE

## Enable PPC405 instructions
option CPU_OPT="-Wa,-m405"

## use a cross compiler
#option CROSS_COMPILE="powerpc-eabi-"

## Use stage 1 initialization code
option CONFIG_USE_INIT=1

## Use chip configuration
option CONFIG_CHIP_CONFIGURE=1

## We don't use compressed image
option CONFIG_COMPRESS=0

## Turn off POST codes
option NO_POST=1

## Enable serial console
option DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
option TTYS0_BASE={UART0_IO_BASE}

## Boot linux from IDE
option CONFIG_IDE_STREAM=1
option IDE_BOOT_DRIVE=0
option IDE_SWAB=1
option IDE_OFFSET=0

option ROM_SIZE=1048576

## Board has fixed size RAM
option EMBEDDED_RAM_SIZE=128*1024*1024

## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00100000

##
## Use a 64K stack
##
option STACK_SIZE=0x10000

##
## Use a 64K heap
##
option HEAP_SIZE=0x10000

##
## System clock
##
option CONFIG_SYS_CLK_FREQ=33

romimage "normal"
	##
	option _ROMBASE=0xfff00000

	## Reset vector address
	option _RESET=0xfffffffc

	## Exception vectors
	option _EXCEPTION_VECTORS=_ROMBASE+0x100

	## linuxBIOS ROM start address
	option _ROMSTART=0xfff03000

	## linuxBIOS C code runs at this location in RAM
	option _RAMBASE=0x00100000

	mainboard embeddedplanet/ep405pc
end

buildrom ./linuxbios.rom ROM_SIZE "normal"