113 lines
3 KiB
C
113 lines
3 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <boardid.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/i2c.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "pmic.h"
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#include "reset.h"
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enum {
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MAX77620_I2C_ADDR = 0x3c,
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MAX77621_CPU_I2C_ADDR = 0x1B,
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MAX77621_GPU_I2C_ADDR = 0x1C,
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};
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struct max77620_init_reg {
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u8 reg;
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u8 val;
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u8 delay;
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};
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static struct max77620_init_reg init_list[] = {
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/* TODO */
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};
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static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val,
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int delay)
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{
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if (i2c_writeb(bus, chip, reg, val)) {
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printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
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__func__, reg, val);
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/* Reset the SoC on any PMIC write error */
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cpu_reset();
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} else {
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if (delay)
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udelay(500);
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}
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}
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void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val,
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int delay)
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{
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pmic_write_reg(bus, MAX77620_I2C_ADDR, reg, val, delay);
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}
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static inline void pmic_write_reg_77621(unsigned bus, uint8_t reg, uint8_t val,
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int delay)
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{
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pmic_write_reg(bus, MAX77621_CPU_I2C_ADDR, reg, val, delay);
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}
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static void pmic_slam_defaults(unsigned bus)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(init_list); i++) {
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struct max77620_init_reg *reg = &init_list[i];
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pmic_write_reg_77620(bus, reg->reg, reg->val, reg->delay);
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}
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}
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void pmic_init(unsigned bus)
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{
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/* Restore PMIC POR defaults, in case kernel changed 'em */
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pmic_slam_defaults(bus);
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/* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
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pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1);
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/* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN -- ??? */
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pmic_write_reg_77620(bus, MAX77620_GPIO1_REG, 0x09, 1);
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/* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
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pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x1c, 1);
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/* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v? */
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pmic_write_reg_77620(bus, MAX77620_CNFG2SD_REG, 0x04, 1);
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pmic_write_reg_77620(bus, MAX77620_SD1_REG, 0x2a, 1);
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/* Max77621 VREG for CPU needs to be set to 0.85V as per SysEng */
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/* Max77621 CPU VREG, register 0, 0.85V = 0x27(0.60625 + (39*6.25mV)) */
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pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0x27, 1);
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pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xa7, 1);
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/* Max77621 CPU VREG DVC, register 1, 0.85V = 0x27 */
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pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0x27, 1);
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pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xa7, 1);
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printk(BIOS_DEBUG, "PMIC init done\n");
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}
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