2015-09-03 18:29:28 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This file assembles the start of the romstage program by the order of the
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* includes. Thus, it's extremely important that one pays very careful
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* attention to the order of the includes. */
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#include <arch/x86/prologue.inc>
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#include <cpu/x86/32bit/entry32.inc>
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#include <cpu/x86/fpu_enable.inc>
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#if IS_ENABLED(CONFIG_SSE)
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#include <cpu/x86/sse_enable.inc>
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#endif
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/*
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2015-09-29 21:54:25 +02:00
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* The assembly.inc is generated based on the requirements of the mainboard.
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2015-09-03 18:29:28 +02:00
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* For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
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* processed by ROMCC and added. In non-ROMCC boards the chipsets'
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* cache-as-ram setup files would be here.
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*/
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2015-09-29 21:54:25 +02:00
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#include <generated/assembly.inc>
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