coreboot-kgpe-d16/targets/embeddedplanet/ep405pc/Config.lb

# Config file for Embedded Planet EP405PC board
# This will make a target directory of ./ep405pc

loadoptions

target ep405pc

uses ARCH 
uses CPU_OPT
uses CROSS_COMPILE 
uses HAVE_OPTION_TABLE
uses CONFIG_COMPRESS 
uses CONFIG_CHIP_CONFIGURE
uses NO_POST
uses CONFIG_IDE_STREAM 
uses CONFIG_SYS_CLK_FREQ
uses IDE_BOOT_DRIVE
uses USE_ELF_BOOT 
uses IDE_SWAB IDE_OFFSET 
uses ROM_SIZE ROM_IMAGE_SIZE 
uses ROM_SECTION_SIZE 
uses ROM_SECTION_OFFSET 
uses _RESET
uses _ROMBASE
uses _RAMBASE
uses CACHE_RAM_BASE 
uses CACHE_RAM_SIZE 
uses STACK_SIZE HEAP_SIZE
uses MAINBOARD 
uses MAINBOARD_PART_NUMBER 
uses MAINBOARD_VENDOR

## Enable PPC405 instructions
option CPU_OPT="-Wa,-m405"

## use a cross compiler
option CROSS_COMPILE="powerpc-eabi-"

## Use chip configuration
option CONFIG_CHIP_CONFIGURE=1

## We don't use compressed image
option CONFIG_COMPRESS=0

## Turn off POST codes
option NO_POST=1

## Boot linux from IDE
option CONFIG_IDE_STREAM=1
option IDE_BOOT_DRIVE=0
option USE_ELF_BOOT=1
option IDE_SWAB=1
option IDE_OFFSET=0

option ROM_SIZE=1048576

## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00100000

## For the trick of using cache as ram
## put the fake ram location at this address
option CACHE_RAM_BASE=0x00200000
option CACHE_RAM_SIZE=0x00004000

##
## Use a 64K stack
##
option STACK_SIZE=0x10000

##
## Use a 64K heap
##
option HEAP_SIZE=0x10000

## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##       
option ROM_SECTION_SIZE=ROM_SIZE
option ROM_SECTION_OFFSET=0

##
## System clock
##
option CONFIG_SYS_CLK_FREQ=33

romimage "normal"
	## Reset vector address
	option _RESET=0xfffffffc

	## linuxBIOS ROM start address
	option _ROMBASE=0xfff00000

	## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
	option ROM_IMAGE_SIZE=49152

	mainboard embeddedplanet/ep405pc
end

buildrom ROM_SIZE "normal"