2006-03-13 22:58:43 +01:00
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#ifndef CPU_AMD_GX2DEF_H
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#define CPU_AMD_GX2DEF_H
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/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
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#define GLCP_CLK_DIS_DELAY 0x4c000008
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#define GLCP_PMCLKDISABLE 0x4c000009
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#define GLCP_DELAY_CONTROLS 0x4c00000f
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#define GLCP_SYS_RSTPLL 0x4c000014
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#define GLCP_DOTPLL 0x4c000015
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/* Upper 32 bits */
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#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
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#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
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#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
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/* Lower 32 bits */
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#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
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#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
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#define GLCP_SYS_RSTPLL_LOCKWAIT 24
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#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
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#define GLCP_SYS_RSTPLL_BYPASS 15
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#define GLCP_SYS_RSTPLL_PD 14
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#define GLCP_SYS_RSTPLL_RESETPLL 13
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#define GLCP_SYS_RSTPLL_DDRMODE 10
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#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
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#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
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#define GLCP_SYS_RSTPLL_CHIP_RESET 0
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#endif /* CPU_AMD_GX2DEF_H */
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