2018-12-05 19:09:04 +01:00
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# x86 architecture documentation
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This section contains documentation about coreboot on x86 architecture.
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2019-02-21 10:27:04 +01:00
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* [x86 PAE support](pae.md)
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2018-12-05 19:09:04 +01:00
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## State of x86_64 support
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At the moment there's no single board that supports x86_64 or to be exact
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`ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`.
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In order to add support for x86_64 the following assumptions are made:
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* The CPU supports long mode
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* All memory returned by malloc must be below 4GiB in physical memory
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* All code that is to be run must be below 4GiB in physical memory
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* The high dword of pointers is always zero
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* The reference implementation is qemu
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* The CPU supports 1GiB hugepages
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2018-12-09 10:48:59 +01:00
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* x86 payloads are loaded below 4GiB in physical memory and are jumped
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to in *protected mode*
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2018-12-05 19:09:04 +01:00
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2019-09-28 17:44:01 +02:00
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## Assuptions for all stages using the reference implementation
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* 0-4GiB are identity mapped using 2MiB-pages as WB
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2018-12-05 19:09:04 +01:00
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* Memory above 4GiB isn't accessible
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2019-09-28 17:44:01 +02:00
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* page tables reside in memory mapped ROM
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* A stage can install new page tables in RAM
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2018-12-05 19:09:04 +01:00
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2019-09-28 17:44:01 +02:00
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## Page tables
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Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes
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the page tables to a file which is then included into the CBFS as file called
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`pagetables`.
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To generate the static page tables it must know the physical address where to
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place the file.
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The page tables contains the following structure:
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* PML4E pointing to PDPE
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* PDPE with *$n* entries each pointing to PDE
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* *$n* PDEs with 512 entries each
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At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
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2018-12-05 19:09:04 +01:00
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## Steps to add basic support for x86_64
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* Add x86_64 toolchain support - *DONE*
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* Fix compilation errors - *DONE*
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* Fix linker errors - *TODO*
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2019-09-28 17:44:01 +02:00
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* Add x86_64 rmodule support - *DONE*
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2019-06-24 18:44:33 +02:00
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* Add x86_64 exception handlers - *DONE*
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2019-09-28 17:44:01 +02:00
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* Setup page tables for long mode - *DONE*
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* Add assembly code for long mode - *DONE*
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2019-09-29 11:08:33 +02:00
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* Add assembly code for SMM - *DONE*
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2018-12-26 15:12:32 +01:00
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* Add assembly code for postcar stage - *DONE*
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2018-12-09 10:48:59 +01:00
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* Add assembly code to return to protected mode - *DONE*
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2018-12-05 19:09:04 +01:00
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* Implement reference code for mainboard `emulation/qemu-q35` - *TODO*
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2020-06-30 20:24:11 +02:00
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## Future work
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1. Fine grained page tables for SMM:
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* Must not have execute and write permissions for the same page.
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* Must allow only that TSEG pages can be marked executable
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* Must reside in SMRAM
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2. Support 64bit PCI BARs above 4GiB
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3. Place and run code above 4GiB
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2018-12-05 19:09:04 +01:00
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## Porting other boards
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* Fix compilation errors
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* Test how well CAR works with x86_64 and paging
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* Improve mode switches
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* Test libgfxinit / VGA Option ROMs / FSP
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