60 lines
1.2 KiB
C
60 lines
1.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/espi.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/smbus.h>
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#include <amdblocks/spi.h>
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#include <console/console.h>
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#include <soc/i2c.h>
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#include <soc/southbridge.h>
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#include <soc/uart.h>
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#include <types.h>
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static void lpc_configure_decodes(void)
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{
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if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
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lpc_enable_port80();
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}
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/* Before console init */
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void fch_pre_init(void)
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{
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lpc_early_init();
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if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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lpc_configure_decodes();
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fch_spi_early_init();
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enable_acpimmio_decode_pm04();
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fch_smbus_init();
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fch_enable_cf9_io();
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fch_enable_legacy_io();
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enable_aoac_devices();
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sb_reset_i2c_slaves();
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/*
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* On reset Range_0 defaults to enabled. We want to start with a clean
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* slate to not have things unexpectedly enabled.
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*/
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clear_uart_legacy_config();
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if (CONFIG(PICASSO_CONSOLE_UART))
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set_uart_config(CONFIG_UART_FOR_CONSOLE);
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}
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/* After console init */
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void fch_early_init(void)
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{
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fch_print_pmxc0_status();
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i2c_soc_early_init();
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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lpc_disable_spi_rom_sharing();
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
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espi_setup();
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espi_configure_decodes();
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}
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}
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