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coreboot-kgpe-d16/src/mainboard/intel/cedarisland_crb/bootblock.c

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mb/intel/cedarisland_crb: Add Cedar Island CRB Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20 20:12:12 +01:00
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#include <superio/aspeed/ast2400/ast2400.h>
#include <superio/aspeed/common/aspeed.h>
mb/intel/cedarisland_crb: use common driver to configure GPIO According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with vendors firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-26 20:08:20 +02:00
#include "include/gpio.h"
mb/intel/cedarisland_crb: Add Cedar Island CRB Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20 20:12:12 +01:00
void bootblock_mainboard_early_init(void)
{
mb/intel/cedarisland_crb: use common driver to configure GPIO According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with vendors firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-26 20:08:20 +02:00
/* Configure Lewisburg PCH GPIOs */
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
mb/intel/cedarisland_crb: Add Cedar Island CRB Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20 20:12:12 +01:00
/* Enable COM1 only */
pcr_write32(PID_DMI, 0x2770, 0);
pcr_write32(PID_DMI, 0x2774, 1);
/* Decode for SuperIO (0x2e) and COM1 (0x3f8) */
pci_mmio_write_config32(PCH_DEV_LPC, 0x80, (1 << 28) | (1 << 16));
const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1);
aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
}
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