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coreboot-kgpe-d16/util/cbfstool/fit.h

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cbfstool: Add update-fit command Add support for filling in the Firmware Interface Table. For now it only supports adding microcode entries. It takes 2 options: 1. Name of file in cbfs where the mircocode is located 2. The number of empty entries in the table. Verified with go firmware tools. Also commented out updating microcode in the bootblock. When romstage runs, the CPUs indicate their microcode is already loaded. Change-Id: Iaccaa9c226ee24868a5f4c0ba79729015d15bbef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2712 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2012-12-15 00:16:21 +01:00
/*
* Firmware Interface Table support.
*
* Copyright (C) 2012 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __CBFSTOOL_FIT_H
#define __CBFSTOOL_FIT_H
cbfstool: Make update-fit action work on new-style images Because new images place the bootblock in a separate region from the primary CBFS, performing an update-fit operation requires reading an additional section and choosing a different destination for the write based on the image type. Since other actions are not affected by these requirements, the logic for the optional read and all writing is implemented in the cbfs_update_fit() function itself, rather than relying on the main() function for writing as the other actions do. Change-Id: I2024c59715120ecc3b9b158e007ebce75acff023 Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-06 23:44:40 +02:00
#include "cbfs_image.h"
#include "common.h"
/*
* Converts between offsets from the start of the specified image region and
* "top-aligned" offsets from the top of the entire flash image. Should work in
* both directions: accepts either type of offset and produces the other type.
* The implementation must have some notion of the flash image's total size.
*/
typedef unsigned (*fit_offset_converter_t)(const struct buffer *region,
unsigned offset);
cbfstool: Update FIT entries in the second bootblock Once a second bootblock has been added using topswap (-j) option, Update the entries in second FIT using -j option with update-fit command. Additionally add a -q option which allows to insert the address of a FMAP region (which should hold a microcode) as the first entry in the second FIT. BUG=None BRANCH=None TEST= Create ROM images with -j options and update FIT using -q option. example: ./build/util/cbfstool/cbfstool coreboot.tmp create \ -M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY build/util/cbfstool/cbfstool coreboot.tmp add \ -f build/cbfs/fallback/bootblock.bin -n bootblock -t \ bootblock -b -49152 -j 0x10000 build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000 build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \ -n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16 build/util/cbfstool/cbfstool coreboot.tmp. update-fit \ -n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A Also try the failure scenarion by providing invalid topswap size. Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/26836 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04 19:32:46 +02:00
/*
* populate FIT with the MCUs prepsent in the blob provided.
*
* first_mcu_addr is an address (in ROM) that will point to a
* microcode patch. When provided, it will be forced as the first
* MCU entry into the FIT located in the topswap bootblock.
*/
cbfstool: Make update-fit action work on new-style images Because new images place the bootblock in a separate region from the primary CBFS, performing an update-fit operation requires reading an additional section and choosing a different destination for the write based on the image type. Since other actions are not affected by these requirements, the logic for the optional read and all writing is implemented in the cbfs_update_fit() function itself, rather than relying on the main() function for writing as the other actions do. Change-Id: I2024c59715120ecc3b9b158e007ebce75acff023 Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-06 23:44:40 +02:00
int fit_update_table(struct buffer *bootblock, struct cbfs_image *image,
cbfstool: Update FIT entries in the second bootblock Once a second bootblock has been added using topswap (-j) option, Update the entries in second FIT using -j option with update-fit command. Additionally add a -q option which allows to insert the address of a FMAP region (which should hold a microcode) as the first entry in the second FIT. BUG=None BRANCH=None TEST= Create ROM images with -j options and update FIT using -q option. example: ./build/util/cbfstool/cbfstool coreboot.tmp create \ -M build/fmap.fmap -r COREBOOT,FW_MAIN_A,FW_MAIN_B,RW_LEGACY build/util/cbfstool/cbfstool coreboot.tmp add \ -f build/cbfs/fallback/bootblock.bin -n bootblock -t \ bootblock -b -49152 -j 0x10000 build/util/cbfstool/cbfstool coreboot.tmp add-master-header -j 0x10000 build/util/cbfstool/cbfstool coreboot.tmp add -f build/cpu_microcode_blob.bin \ -n cpu_microcode_blob.bin -t microcode -r COREBOOT -a 16 build/util/cbfstool/cbfstool coreboot.tmp. update-fit \ -n cpu_microcode_blob.bin -x 4 -j 0x10000 -q FW_MAIN_A Also try the failure scenarion by providing invalid topswap size. Change-Id: I9a417031c279038903cdf1761a791f2da0fe8644 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/26836 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04 19:32:46 +02:00
const char *microcode_blob_name, int empty_entries,
fit_offset_converter_t offset_fn,
uint32_t topswap_size, uint32_t first_mcu_addr);
cbfstool: Add update-fit command Add support for filling in the Firmware Interface Table. For now it only supports adding microcode entries. It takes 2 options: 1. Name of file in cbfs where the mircocode is located 2. The number of empty entries in the table. Verified with go firmware tools. Also commented out updating microcode in the bootblock. When romstage runs, the CPUs indicate their microcode is already loaded. Change-Id: Iaccaa9c226ee24868a5f4c0ba79729015d15bbef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2712 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2012-12-15 00:16:21 +01:00
#endif