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coreboot-kgpe-d16/configs/config.msi_ms7d25

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mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-04-07 15:16:46 +02:00
CONFIG_VENDOR_MSI=y
CONFIG_CBFS_SIZE=0x1000000
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_TIANOCORE_BOOT_TIMEOUT=3
CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
mb/msi/ms7d25: Configure PCIe Root Ports Add the full PCIe root port configuration. Proper initialization of the root ports depends on the correct GPIO programming including virtual wires. Do not program the CLKREQ signals in coreboot to let FSP detect and configure CLKREQ pads. Otherwise the CLKREQ pads are reprogrammed by FSP despite having GpioOverride=1. The pads that should not be touched by coreboot are left commented in the board GPIO file. CLKREQ reprogramming caused undefined behavior when ASPM and Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed a lot of exceptions and simply halted). TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots populated and check if they are detected and functional in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-15 18:19:19 +02:00
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-04-07 15:16:46 +02:00
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_POST_DEVICE_PCI_PCIE=y
CONFIG_POST_IO_PORT=0x80
CONFIG_PAYLOAD_TIANOCORE=y
CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
CONFIG_TIANOCORE_CBMEM_LOGGING=y
CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000