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coreboot-kgpe-d16/src/soc/amd/picasso/uart.c

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soc/amd: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-04 18:50:57 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 22:55:16 +02:00
#include <console/uart.h>
soc/amd/picasso: Update UARTs Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-20 18:29:29 +02:00
#include <commonlib/helpers.h>
Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-03 07:03:27 +01:00
#include <device/mmio.h>
soc/amd/picasso: Update UARTs Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-20 18:29:29 +02:00
#include <amdblocks/gpio_banks.h>
#include <amdblocks/acpimmio.h>
soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 22:55:16 +02:00
#include <soc/southbridge.h>
soc/amd/picasso: Update UARTs Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-20 18:29:29 +02:00
#include <soc/gpio.h>
static const struct _uart_info {
uintptr_t base;
struct soc_amd_gpio mux[2];
} uart_info[] = {
[0] = { APU_UART0_BASE, {
PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
} },
[1] = { APU_UART1_BASE, {
PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),
PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
} },
[2] = { APU_UART2_BASE, {
PAD_NF(GPIO_137, UART2_TXD, PULL_NONE),
PAD_NF(GPIO_135, UART2_RXD, PULL_NONE),
} },
[3] = { APU_UART3_BASE, {
PAD_NF(GPIO_140, UART3_TXD, PULL_NONE),
PAD_NF(GPIO_142, UART3_RXD, PULL_NONE),
} },
};
soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 22:55:16 +02:00
soc/amd/picasso: fix build if PICASSO_UART is unset This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 09:16:26 +02:00
/*
soc/amd/picasso: rename PICASSO_UART Kconfig option The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16 15:35:20 +02:00
* Don't provide uart_platform_base and uart_platform_refclk functions if PICASSO_CONSOLE_UART
soc/amd/picasso: fix build if PICASSO_UART is unset This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 09:16:26 +02:00
* isn't selected. Those two functions are used by the console UART driver and need to be
* provided exactly once and only by the UART that is used for console.
*
* TODO: Replace the #if block by factoring out the two functions into a different compilation
* unit.
*/
soc/amd/picasso: rename PICASSO_UART Kconfig option The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16 15:35:20 +02:00
#if CONFIG(PICASSO_CONSOLE_UART)
soc/amd/picasso: fix build if PICASSO_UART is unset This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 09:16:26 +02:00
soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 22:55:16 +02:00
uintptr_t uart_platform_base(int idx)
{
soc/amd/picasso/uart: fix possible out of bounds access Found-by: Coverity CID 1429769, 1429777 Change-Id: Ide188379a34c769c929bf7832fd94a7004c09a64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 19:39:51 +02:00
if (idx < 0 || idx >= ARRAY_SIZE(uart_info))
soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 22:55:16 +02:00
return 0;
soc/amd/picasso: Update UARTs Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-20 18:29:29 +02:00
return uart_info[idx].base;
}
soc/amd/picasso: fix build if PICASSO_UART is unset This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 09:16:26 +02:00
unsigned int uart_platform_refclk(void)
{
return CONFIG(PICASSO_UART_48MZ) ? 48000000 : 115200 * 16;
}
soc/amd/picasso: rename PICASSO_UART Kconfig option The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16 15:35:20 +02:00
#endif /* PICASSO_CONSOLE_UART */
soc/amd/picasso: fix build if PICASSO_UART is unset This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 09:16:26 +02:00
soc/amd/picasso: Explicitly disable legacy UART The legacy UARTs are supposed to default to off according to the documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0 is enabled after reset. The PSP might be enabling it or the documentation might be wrong. Having it enabled causes problems though. We have ACPI nodes defining MMIO UARTs, and the kernel also probes for legacy UARTs. This results in two drivers accessing the same device, one via MMIO and one via IO. I suspect this was the cause of the garbage serial output. Before the change you would see the following in the console: [ 0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A After this change, we no longer see it. BUG=b:152079780, b:157858890 TEST=Boot trembyle and make sure serial is still working. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-12 00:27:49 +02:00
void clear_uart_legacy_config(void)
{
write16((void *)FCH_UART_LEGACY_DECODE, 0);
}
soc/amd/picasso: Update UARTs Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-20 18:29:29 +02:00
void set_uart_config(int idx)
{
uint32_t uart_ctrl;
uint16_t uart_leg;
soc/amd/picasso/uart: fix possible out of bounds access Found-by: Coverity CID 1429769, 1429777 Change-Id: Ide188379a34c769c929bf7832fd94a7004c09a64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 19:39:51 +02:00
if (idx < 0 || idx >= ARRAY_SIZE(uart_info))
soc/amd/picasso: Update UARTs Add a function to uart.c to ensure the right IOMux settings are programmed for the console UART. Update Kconfig to reflect the new addresses. Give the user the ability to downclock the UARTs' refclock to 1.8342MHz. Add the abiltiy to use an APU UART at a legacy I/O address. Update the AOAC register configuration for the two additional UARTs. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-20 18:29:29 +02:00
return;
program_gpios(uart_info[idx].mux, 2);
if (CONFIG(PICASSO_UART_1_8MZ)) {
uart_ctrl = sm_pci_read32(SMB_UART_CONFIG);
uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx);
sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
}
if (CONFIG(PICASSO_UART_LEGACY) && idx != 3) {
/* Force 3F8 if idx=0, 2F8 if idx=1, 3E8 if idx=2 */
/* TODO: make clearer once PPR is updated */
uart_leg = (idx << 8) | (idx << 10) | (idx << 12) | (idx << 14);
if (idx == 0)
uart_leg |= 1 << FCH_LEGACY_3F8_SH;
else if (idx == 1)
uart_leg |= 1 << FCH_LEGACY_2F8_SH;
else if (idx == 2)
uart_leg |= 1 << FCH_LEGACY_3E8_SH;
write16((void *)FCH_UART_LEGACY_DECODE, uart_leg);
}
soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-22 22:55:16 +02:00
}
soc/amd/picasso: Add device operations for UART MMIO devices This change adds device_operations for UART MMIO devices that provides following operations: 1. uart_acpi_name: Returns ACPI name of UART device. Generation of UART device node is not yet moved to SSDT, but will be done in follow-up CLs. 2. scan_bus: Uses scan_static_bus to scan devices added under the UART devices. This allows mainboard to add devices under the UART MMIO device. Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-04 01:50:32 +02:00
static const char *uart_acpi_name(const struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_UART0_BASE:
return "FUR0";
case APU_UART1_BASE:
return "FUR1";
case APU_UART2_BASE:
return "FUR2";
case APU_UART3_BASE:
return "FUR3";
default:
return NULL;
}
}
struct device_operations picasso_uart_mmio_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.scan_bus = scan_static_bus,
.acpi_name = uart_acpi_name,
};
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