720 lines
21 KiB
C
720 lines
21 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*-----------------------------------------------------------------------------
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* M O D U L E S U S E D
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*-----------------------------------------------------------------------------
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*/
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#include <stdint.h>
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#include <string.h>
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#include "agesawrapper.h"
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#include "BiosCallOuts.h"
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#include "cpuRegisters.h"
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#include "cpuCacheInit.h"
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#include "cpuApicUtilities.h"
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#include "cpuEarlyInit.h"
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#include "cpuLateInit.h"
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#include "Dispatcher.h"
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#include "cpuCacheInit.h"
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#include "heapManager.h"
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#include "amdlib.h"
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#include "PlatformGnbPcieComplex.h"
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#include "Filecode.h"
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#include <arch/io.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include <cbmem.h>
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#include <arch/acpi.h>
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#define FILECODE UNASSIGNED_FILE_FILECODE
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/*------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*------------------------------------------------------------------------------
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*/
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#define MMCONF_ENABLE 1
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/* ACPI table pointers returned by AmdInitLate */
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VOID *DmiTable = NULL;
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VOID *AcpiPstate = NULL;
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VOID *AcpiSrat = NULL;
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VOID *AcpiSlit = NULL;
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VOID *AcpiWheaMce = NULL;
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VOID *AcpiWheaCmc = NULL;
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VOID *AcpiAlib = NULL;
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/*------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*------------------------------------------------------------------------------
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*/
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/*------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*------------------------------------------------------------------------------
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*/
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/*------------------------------------------------------------------------------
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* E X P O R T E D F U N C T I O N S
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*------------------------------------------------------------------------------
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*/
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/*------------------------------------------------------------------------------
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* L O C A L F U N C T I O N S
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*------------------------------------------------------------------------------
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*/
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UINT32
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agesawrapper_amdinitcpuio (
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VOID
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)
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{
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AGESA_STATUS Status;
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
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PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
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PciData |= 1 << 7; // set NP (non-posted) bit
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
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PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; // last address before non-posted range
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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Status = AGESA_SUCCESS;
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return (UINT32)Status;
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}
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UINT32
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agesawrapper_amdinitmmio (
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VOID
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)
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{
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AGESA_STATUS Status;
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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UINT8 BusRangeVal = 0;
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UINT8 BusNum;
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UINT8 Index;
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/*
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Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
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Address MSR register.
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*/
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for (Index = 0; Index < 8; Index++) {
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BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
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if (BusNum == 1) {
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BusRangeVal = Index;
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break;
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}
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}
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MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
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LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
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/*
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Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
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*/
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LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
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MsrReg = MsrReg | 0x0000400000000000ull;
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LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
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/* Set Ontario Link Data */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
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PciData = 0x01308002;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
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PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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Status = AGESA_SUCCESS;
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return (UINT32)Status;
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}
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UINT32
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agesawrapper_amdinitreset (
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VOID
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)
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{
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AGESA_STATUS status;
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AMD_INTERFACE_PARAMS AmdParamStruct;
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AMD_RESET_PARAMS AmdResetParams;
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LibAmdMemFill (&AmdParamStruct,
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0,
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sizeof (AMD_INTERFACE_PARAMS),
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&(AmdParamStruct.StdHeader));
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LibAmdMemFill (&AmdResetParams,
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0,
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sizeof (AMD_RESET_PARAMS),
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&(AmdResetParams.StdHeader));
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AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
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AmdParamStruct.AllocationMethod = ByHost;
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AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
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AmdParamStruct.NewStructPtr = &AmdResetParams;
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AmdParamStruct.StdHeader.AltImageBasePtr = 0;
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AmdParamStruct.StdHeader.CalloutPtr = NULL;
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AmdParamStruct.StdHeader.Func = 0;
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AmdParamStruct.StdHeader.ImageBasePtr = 0;
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AmdCreateStruct (&AmdParamStruct);
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AmdResetParams.HtConfig.Depth = 0;
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status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
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if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
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AmdReleaseStruct (&AmdParamStruct);
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return (UINT32)status;
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}
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UINT32
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agesawrapper_amdinitearly (
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VOID
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)
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{
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AGESA_STATUS status;
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AMD_INTERFACE_PARAMS AmdParamStruct;
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AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
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LibAmdMemFill (&AmdParamStruct,
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0,
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sizeof (AMD_INTERFACE_PARAMS),
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&(AmdParamStruct.StdHeader));
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AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
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AmdParamStruct.AllocationMethod = PreMemHeap;
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AmdParamStruct.StdHeader.AltImageBasePtr = 0;
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AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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AmdParamStruct.StdHeader.Func = 0;
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AmdParamStruct.StdHeader.ImageBasePtr = 0;
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AmdCreateStruct (&AmdParamStruct);
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AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
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OemCustomizeInitEarly (AmdEarlyParamsPtr);
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status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
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if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
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AmdReleaseStruct (&AmdParamStruct);
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return (UINT32)status;
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}
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UINT32 GetHeapBase(
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AMD_CONFIG_PARAMS *StdHeader
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)
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{
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UINT32 heap;
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#if CONFIG_HAVE_ACPI_RESUME
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/* Both romstage and ramstage has this S3 detect. */
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if (acpi_get_sleep_type() == 3)
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heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */
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else
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#endif
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heap = BIOS_HEAP_START_ADDRESS; /* low mem */
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return heap;
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}
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UINT32
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agesawrapper_amdinitpost (
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VOID
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)
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{
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AGESA_STATUS status;
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UINT16 i;
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UINT32 *HeadPtr;
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AMD_INTERFACE_PARAMS AmdParamStruct;
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BIOS_HEAP_MANAGER *BiosManagerPtr;
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LibAmdMemFill (&AmdParamStruct,
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0,
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sizeof (AMD_INTERFACE_PARAMS),
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&(AmdParamStruct.StdHeader));
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AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
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AmdParamStruct.AllocationMethod = PreMemHeap;
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AmdParamStruct.StdHeader.AltImageBasePtr = 0;
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AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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AmdParamStruct.StdHeader.Func = 0;
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AmdParamStruct.StdHeader.ImageBasePtr = 0;
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AmdCreateStruct (&AmdParamStruct);
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status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
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if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
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AmdReleaseStruct (&AmdParamStruct);
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/* Initialize heap space */
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BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader);
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HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
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for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
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*HeadPtr = 0x00000000;
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HeadPtr++;
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}
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BiosManagerPtr->StartOfAllocatedNodes = 0;
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BiosManagerPtr->StartOfFreedNodes = 0;
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return (UINT32)status;
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}
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UINT32
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agesawrapper_amdinitenv (
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VOID
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)
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{
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AGESA_STATUS status;
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AMD_INTERFACE_PARAMS AmdParamStruct;
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PCI_ADDR PciAddress;
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UINT32 PciValue;
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LibAmdMemFill (&AmdParamStruct,
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0,
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sizeof (AMD_INTERFACE_PARAMS),
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&(AmdParamStruct.StdHeader));
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AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
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AmdParamStruct.AllocationMethod = PostMemDram;
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AmdParamStruct.StdHeader.AltImageBasePtr = 0;
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AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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AmdParamStruct.StdHeader.Func = 0;
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AmdParamStruct.StdHeader.ImageBasePtr = 0;
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AmdCreateStruct (&AmdParamStruct);
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status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
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if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
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/* Initialize Subordinate Bus Number and Secondary Bus Number
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* In platform BIOS this address is allocated by PCI enumeration code
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Modify D1F0x18
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*/
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PciAddress.Address.Bus = 0;
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PciAddress.Address.Device = 1;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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/* Write to D1F0x18 */
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LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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PciValue |= 0x00010100;
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LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
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/* Initialize GMM Base Address for Legacy Bridge Mode
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* Modify B1D5F0x18
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*/
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PciAddress.Address.Bus = 1;
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PciAddress.Address.Device = 5;
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PciAddress.Address.Function = 0;
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PciAddress.Address.Register = 0x18;
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|
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
PciValue |= 0x96000000;
|
||
|
|
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
|
||
|
|
/* Initialize FB Base Address for Legacy Bridge Mode
|
||
|
|
* Modify B1D5F0x10
|
||
|
|
*/
|
||
|
|
PciAddress.Address.Register = 0x10;
|
||
|
|
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
PciValue |= 0x80000000;
|
||
|
|
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
|
||
|
|
/* Initialize GMM Base Address for Pcie Mode
|
||
|
|
* Modify B0D1F0x18
|
||
|
|
*/
|
||
|
|
PciAddress.Address.Bus = 0;
|
||
|
|
PciAddress.Address.Device = 1;
|
||
|
|
PciAddress.Address.Function = 0;
|
||
|
|
PciAddress.Address.Register = 0x18;
|
||
|
|
|
||
|
|
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
PciValue |= 0x96000000;
|
||
|
|
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
|
||
|
|
/* Initialize FB Base Address for Pcie Mode
|
||
|
|
* Modify B0D1F0x10
|
||
|
|
*/
|
||
|
|
PciAddress.Address.Register = 0x10;
|
||
|
|
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
PciValue |= 0x80000000;
|
||
|
|
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
|
||
|
|
/* Initialize MMIO Base and Limit Address
|
||
|
|
* Modify B0D1F0x20
|
||
|
|
*/
|
||
|
|
PciAddress.Address.Bus = 0;
|
||
|
|
PciAddress.Address.Device = 1;
|
||
|
|
PciAddress.Address.Function = 0;
|
||
|
|
PciAddress.Address.Register = 0x20;
|
||
|
|
|
||
|
|
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
PciValue |= 0x96009600;
|
||
|
|
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
|
||
|
|
/* Initialize MMIO Prefetchable Memory Limit and Base
|
||
|
|
* Modify B0D1F0x24
|
||
|
|
*/
|
||
|
|
PciAddress.Address.Register = 0x24;
|
||
|
|
LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
PciValue |= 0x8FF18001;
|
||
|
|
LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
|
||
|
|
AmdReleaseStruct (&AmdParamStruct);
|
||
|
|
|
||
|
|
return (UINT32)status;
|
||
|
|
}
|
||
|
|
|
||
|
|
VOID *
|
||
|
|
agesawrapper_getlateinitptr (
|
||
|
|
int pick
|
||
|
|
)
|
||
|
|
{
|
||
|
|
switch (pick) {
|
||
|
|
case PICK_DMI:
|
||
|
|
return DmiTable;
|
||
|
|
case PICK_PSTATE:
|
||
|
|
return AcpiPstate;
|
||
|
|
case PICK_SRAT:
|
||
|
|
return AcpiSrat;
|
||
|
|
case PICK_SLIT:
|
||
|
|
return AcpiSlit;
|
||
|
|
case PICK_WHEA_MCE:
|
||
|
|
return AcpiWheaMce;
|
||
|
|
case PICK_WHEA_CMC:
|
||
|
|
return AcpiWheaCmc;
|
||
|
|
case PICK_ALIB:
|
||
|
|
return AcpiAlib;
|
||
|
|
default:
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
UINT32
|
||
|
|
agesawrapper_amdinitmid (
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
{
|
||
|
|
AGESA_STATUS status;
|
||
|
|
AMD_INTERFACE_PARAMS AmdParamStruct;
|
||
|
|
|
||
|
|
/* Enable MMIO on AMD CPU Address Map Controller */
|
||
|
|
agesawrapper_amdinitcpuio ();
|
||
|
|
|
||
|
|
LibAmdMemFill (&AmdParamStruct,
|
||
|
|
0,
|
||
|
|
sizeof (AMD_INTERFACE_PARAMS),
|
||
|
|
&(AmdParamStruct.StdHeader));
|
||
|
|
|
||
|
|
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
|
||
|
|
AmdParamStruct.AllocationMethod = PostMemDram;
|
||
|
|
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
|
||
|
|
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
|
||
|
|
AmdParamStruct.StdHeader.Func = 0;
|
||
|
|
AmdParamStruct.StdHeader.ImageBasePtr = 0;
|
||
|
|
|
||
|
|
AmdCreateStruct (&AmdParamStruct);
|
||
|
|
|
||
|
|
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
|
||
|
|
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
|
||
|
|
AmdReleaseStruct (&AmdParamStruct);
|
||
|
|
|
||
|
|
return (UINT32)status;
|
||
|
|
}
|
||
|
|
|
||
|
|
UINT32
|
||
|
|
agesawrapper_amdinitlate (
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
{
|
||
|
|
AGESA_STATUS Status;
|
||
|
|
AMD_INTERFACE_PARAMS AmdParamStruct;
|
||
|
|
AMD_LATE_PARAMS * AmdLateParamsPtr;
|
||
|
|
|
||
|
|
LibAmdMemFill (&AmdParamStruct,
|
||
|
|
0,
|
||
|
|
sizeof (AMD_INTERFACE_PARAMS),
|
||
|
|
&(AmdParamStruct.StdHeader));
|
||
|
|
|
||
|
|
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
|
||
|
|
AmdParamStruct.AllocationMethod = PostMemDram;
|
||
|
|
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
|
||
|
|
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
|
||
|
|
AmdParamStruct.StdHeader.Func = 0;
|
||
|
|
AmdParamStruct.StdHeader.ImageBasePtr = 0;
|
||
|
|
|
||
|
|
AmdCreateStruct (&AmdParamStruct);
|
||
|
|
AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
|
||
|
|
|
||
|
|
printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
|
||
|
|
|
||
|
|
Status = AmdInitLate (AmdLateParamsPtr);
|
||
|
|
if (Status != AGESA_SUCCESS) {
|
||
|
|
agesawrapper_amdreadeventlog();
|
||
|
|
ASSERT(Status == AGESA_SUCCESS);
|
||
|
|
}
|
||
|
|
|
||
|
|
DmiTable = AmdLateParamsPtr->DmiTable;
|
||
|
|
AcpiPstate = AmdLateParamsPtr->AcpiPState;
|
||
|
|
AcpiSrat = AmdLateParamsPtr->AcpiSrat;
|
||
|
|
AcpiSlit = AmdLateParamsPtr->AcpiSlit;
|
||
|
|
AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
|
||
|
|
AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
|
||
|
|
AcpiAlib = AmdLateParamsPtr->AcpiAlib;
|
||
|
|
|
||
|
|
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
|
||
|
|
" DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n"
|
||
|
|
" Mce:%p\n Cmc:%p\n Alib:%p\n",
|
||
|
|
__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
|
||
|
|
AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
|
||
|
|
|
||
|
|
/* Don't release the structure until coreboot has copied the ACPI tables.
|
||
|
|
* AmdReleaseStruct (&AmdLateParams);
|
||
|
|
*/
|
||
|
|
|
||
|
|
return (UINT32)Status;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if CONFIG_HAVE_ACPI_RESUME
|
||
|
|
UINT32
|
||
|
|
agesawrapper_amdinitresume (
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
{
|
||
|
|
AGESA_STATUS status;
|
||
|
|
AMD_INTERFACE_PARAMS AmdParamStruct;
|
||
|
|
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
|
||
|
|
S3_DATA_TYPE S3DataType;
|
||
|
|
|
||
|
|
LibAmdMemFill (&AmdParamStruct,
|
||
|
|
0,
|
||
|
|
sizeof (AMD_INTERFACE_PARAMS),
|
||
|
|
&(AmdParamStruct.StdHeader));
|
||
|
|
|
||
|
|
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
|
||
|
|
AmdParamStruct.AllocationMethod = PreMemHeap;
|
||
|
|
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
|
||
|
|
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
|
||
|
|
AmdParamStruct.StdHeader.Func = 0;
|
||
|
|
AmdParamStruct.StdHeader.ImageBasePtr = 0;
|
||
|
|
AmdCreateStruct (&AmdParamStruct);
|
||
|
|
|
||
|
|
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
|
||
|
|
|
||
|
|
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
|
||
|
|
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
|
||
|
|
S3DataType = S3DataTypeNonVolatile;
|
||
|
|
|
||
|
|
OemAgesaGetS3Info (S3DataType,
|
||
|
|
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
|
||
|
|
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
|
||
|
|
|
||
|
|
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
|
||
|
|
|
||
|
|
if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
|
||
|
|
AmdReleaseStruct (&AmdParamStruct);
|
||
|
|
|
||
|
|
return (UINT32)status;
|
||
|
|
}
|
||
|
|
|
||
|
|
UINT32
|
||
|
|
agesawrapper_amds3laterestore (
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
{
|
||
|
|
AGESA_STATUS Status;
|
||
|
|
AMD_INTERFACE_PARAMS AmdInterfaceParams;
|
||
|
|
AMD_S3LATE_PARAMS AmdS3LateParams;
|
||
|
|
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
|
||
|
|
S3_DATA_TYPE S3DataType;
|
||
|
|
|
||
|
|
LibAmdMemFill (&AmdS3LateParams,
|
||
|
|
0,
|
||
|
|
sizeof (AMD_S3LATE_PARAMS),
|
||
|
|
&(AmdS3LateParams.StdHeader));
|
||
|
|
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
|
||
|
|
AmdInterfaceParams.AllocationMethod = ByHost;
|
||
|
|
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
|
||
|
|
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
|
||
|
|
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
|
||
|
|
AmdS3LateParamsPtr = &AmdS3LateParams;
|
||
|
|
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
|
||
|
|
|
||
|
|
AmdCreateStruct (&AmdInterfaceParams);
|
||
|
|
|
||
|
|
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
|
||
|
|
S3DataType = S3DataTypeVolatile;
|
||
|
|
|
||
|
|
OemAgesaGetS3Info (S3DataType,
|
||
|
|
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
|
||
|
|
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
|
||
|
|
|
||
|
|
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
|
||
|
|
if (Status != AGESA_SUCCESS) {
|
||
|
|
agesawrapper_amdreadeventlog();
|
||
|
|
ASSERT(Status == AGESA_SUCCESS);
|
||
|
|
}
|
||
|
|
|
||
|
|
return (UINT32)Status;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifndef __PRE_RAM__
|
||
|
|
UINT32
|
||
|
|
agesawrapper_amdS3Save (
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
{
|
||
|
|
AGESA_STATUS Status;
|
||
|
|
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
|
||
|
|
AMD_INTERFACE_PARAMS AmdInterfaceParams;
|
||
|
|
S3_DATA_TYPE S3DataType;
|
||
|
|
|
||
|
|
LibAmdMemFill (&AmdInterfaceParams,
|
||
|
|
0,
|
||
|
|
sizeof (AMD_INTERFACE_PARAMS),
|
||
|
|
&(AmdInterfaceParams.StdHeader));
|
||
|
|
|
||
|
|
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
|
||
|
|
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
|
||
|
|
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
|
||
|
|
AmdInterfaceParams.AllocationMethod = PostMemDram;
|
||
|
|
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
|
||
|
|
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
|
||
|
|
AmdInterfaceParams.StdHeader.Func = 0;
|
||
|
|
AmdCreateStruct(&AmdInterfaceParams);
|
||
|
|
|
||
|
|
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
|
||
|
|
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
|
||
|
|
|
||
|
|
Status = AmdS3Save (AmdS3SaveParamsPtr);
|
||
|
|
if (Status != AGESA_SUCCESS) {
|
||
|
|
agesawrapper_amdreadeventlog();
|
||
|
|
ASSERT(Status == AGESA_SUCCESS);
|
||
|
|
}
|
||
|
|
|
||
|
|
S3DataType = S3DataTypeNonVolatile;
|
||
|
|
|
||
|
|
Status = OemAgesaSaveS3Info (
|
||
|
|
S3DataType,
|
||
|
|
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
|
||
|
|
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
|
||
|
|
|
||
|
|
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
|
||
|
|
S3DataType = S3DataTypeVolatile;
|
||
|
|
|
||
|
|
Status = OemAgesaSaveS3Info (
|
||
|
|
S3DataType,
|
||
|
|
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
|
||
|
|
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
OemAgesaSaveMtrr();
|
||
|
|
AmdReleaseStruct (&AmdInterfaceParams);
|
||
|
|
|
||
|
|
return (UINT32)Status;
|
||
|
|
}
|
||
|
|
#endif /* #ifndef __PRE_RAM__ */
|
||
|
|
#endif /* CONFIG_HAVE_ACPI_RESUME */
|
||
|
|
|
||
|
|
UINT32
|
||
|
|
agesawrapper_amdlaterunaptask (
|
||
|
|
UINT32 Func,
|
||
|
|
UINT32 Data,
|
||
|
|
VOID *ConfigPtr
|
||
|
|
)
|
||
|
|
{
|
||
|
|
AGESA_STATUS Status;
|
||
|
|
AP_EXE_PARAMS ApExeParams;
|
||
|
|
|
||
|
|
LibAmdMemFill (&ApExeParams,
|
||
|
|
0,
|
||
|
|
sizeof (AP_EXE_PARAMS),
|
||
|
|
&(ApExeParams.StdHeader));
|
||
|
|
|
||
|
|
ApExeParams.StdHeader.AltImageBasePtr = 0;
|
||
|
|
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
|
||
|
|
ApExeParams.StdHeader.Func = 0;
|
||
|
|
ApExeParams.StdHeader.ImageBasePtr = 0;
|
||
|
|
ApExeParams.FunctionNumber = Func;
|
||
|
|
ApExeParams.RelatedDataBlock = ConfigPtr;
|
||
|
|
|
||
|
|
Status = AmdLateRunApTask (&ApExeParams);
|
||
|
|
if (Status != AGESA_SUCCESS) {
|
||
|
|
agesawrapper_amdreadeventlog();
|
||
|
|
ASSERT(Status == AGESA_SUCCESS);
|
||
|
|
}
|
||
|
|
|
||
|
|
return (UINT32)Status;
|
||
|
|
}
|
||
|
|
|
||
|
|
UINT32
|
||
|
|
agesawrapper_amdreadeventlog (
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
{
|
||
|
|
AGESA_STATUS Status;
|
||
|
|
EVENT_PARAMS AmdEventParams;
|
||
|
|
|
||
|
|
LibAmdMemFill (&AmdEventParams,
|
||
|
|
0,
|
||
|
|
sizeof (EVENT_PARAMS),
|
||
|
|
&(AmdEventParams.StdHeader));
|
||
|
|
|
||
|
|
AmdEventParams.StdHeader.AltImageBasePtr = 0;
|
||
|
|
AmdEventParams.StdHeader.CalloutPtr = NULL;
|
||
|
|
AmdEventParams.StdHeader.Func = 0;
|
||
|
|
AmdEventParams.StdHeader.ImageBasePtr = 0;
|
||
|
|
Status = AmdReadEventLog (&AmdEventParams);
|
||
|
|
while (AmdEventParams.EventClass != 0) {
|
||
|
|
printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
|
||
|
|
printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
|
||
|
|
printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
|
||
|
|
Status = AmdReadEventLog (&AmdEventParams);
|
||
|
|
}
|
||
|
|
|
||
|
|
return (UINT32)Status;
|
||
|
|
}
|