137 lines
5.6 KiB
Markdown
137 lines
5.6 KiB
Markdown
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# Configuring a mainboard's GPIOs in coreboot
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## Introduction
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Every mainboard needs to appropriately configure its General Purpose Inputs /
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Outputs (GPIOs). There are many facets of this issue, including which boot
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stage a GPIO might need to be configured.
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## Boot stages
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Typically, coreboot does most of its non-memory related initialization work in
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ramstage, when DRAM is available for use. Hence, the bulk of a mainboard's GPIOs
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are configured in this stage. However, some boards might need a few GPIOs
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configured before that; think of memory strapping pins which indicate what kind
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of DRAM is installed. These pins might need to be read before initializing the
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memory, so these GPIOs are then typically configured in bootblock or romstage.
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## Configuration
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Most mainboards will have a ``gpio.c`` file in their mainboard directory. This
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file typically contains tables which describe the configuration of the GPIO
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registers. Since these registers could be different on a per-SoC or per
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SoC-family basis, you may need to consult the datasheet for your SoC to find out
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how to appropriately set these registers. In addition, some mainboards are
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based on a baseboard/variant model, where several variant mainboards may share a
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lot of their circuitry and ICs and the commonality between the boards is
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collected into a virtual ``baseboard.`` In that case, the GPIOs which are shared
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between multiple boards are placed in the baseboard's ``gpio.c` file, while the
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ones that are board-specific go into each variant's ``gpio.c`` file.
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## Intel SoCs
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Many newer Intel SoCs share a common IP block for GPIOs, and that commonality
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has been taken advantage of in coreboot, which has a large set of macros that
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can be used to describe the configuration of each GPIO pad. This file lives in
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``src/soc/intel/common/block/include/intelblocks/gpio_defs.h``.
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### Older Intel SoCs
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Baytrail and Braswell, for example, simply expect the mainboard to supply a
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callback, `mainboard_get_gpios` which returns an array of `struct soc_gpio`
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objects, defining the configuration of each pin.
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### AMD SoCs
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Some AMD SoCs use a list of `struct soc_amd_gpio` objects to define the
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register values configuring each pin, similar to Intel.
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### Register details
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GPIO configuration registers typically control properties such as:
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1. Input / Output
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2. Pullups / Pulldowns
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3. Termination
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4. Tx / Rx Disable
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5. Which reset signal to use
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6. Native Function / IO
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7. Interrupts
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* IRQ routing (e.g. on x86, APIC, SCI, SMI)
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* Edge or Level Triggered
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* Active High or Active Low
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8. Debouncing
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## Configuring GPIOs for pre-ramstage
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coreboot provides for several SoC-specific and mainboard-specific callbacks at
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specific points in time, such as bootblock-early, bootblock, romstage entry,
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pre-silicon init, pre-RAM init, or post-RAM init. The GPIOs that are
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configured in either bootblock or romstage, depending on when they are needed,
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are denoted the "early" GPIOs. Some mainboard will use
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``bootblock_mainboard_init()`` to configure their early GPIOs, and this is
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probably a good place to start. Many mainboards will declare their GPIO
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configuration as structs, i.e. (Intel),
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```C
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struct pad_config {
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/* offset of pad within community */
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int pad;
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/* Pad config data corresponding to DW0, DW1,.... */
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uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];
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};
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```
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and will usually place these in an array, one for each pad to be configured.
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Mainboards using Intel SoCs can use a library which combines common
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configurations together into a set of macros, e.g.,
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```C
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/* Native function configuration */
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#define PAD_CFG_NF(pad, pull, rst, func)
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/*
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* Set native function with RX Level/Edge configuration and disable
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* input/output buffer if necessary
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*/
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#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig)
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/* General purpose output, no pullup/down. */
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#define PAD_CFG_GPO(pad, val, rst)
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/* General purpose output, with termination specified */
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#define PAD_CFG_TERM_GPO(pad, val, pull, rst)
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/* General purpose output, no pullup/down. */
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#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull)
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/* General purpose input */
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#define PAD_CFG_GPI(pad, pull, rst)
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```
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etc.
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## Configuring GPIOs for ramstage and beyond...
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In ramstage, most mainboards will configure the rest of their GPIOs for the
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function they will be performing while the device is active. The goal is the
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same as above in bootblock; another ``static const`` array is created, and the
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rest of the GPIO registers are programmed.
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In the baseboard/variant model described above, the baseboard will provide the
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configuration for the GPIOs which are configured identically between variants,
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and will provide a mechanism for a variant to override the baseboard's
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configuration. This is usually done via two tables: the baseboard table and the
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variant's override table.
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This configuration is often hooked into the mainboard's `enable_dev` callback,
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defined in its `struct chip_operations`.
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## Potential issues (gotchas!)
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There are a couple of configurations that you need to especially careful about,
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as they can have a large impact on your mainboard.
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The first is configuring a pin as an output, when it was designed to be an
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input. There is a real risk in this case of short-circuiting a component which
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could cause catastrophic failures, up to and including your mainboard!
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The other configuration option to watch out for deals with unconnected GPIOs.
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If no pullup or pulldown is declared with these, they may end up "floating",
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i.e., not at logical high or logical low. This can cause problems such as
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unwanted power consumption or not reading the pin correctly, if it was intended
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to be strapped.
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