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mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-11 04:00:07 +02:00
FLASH@0xFF000000 16M {
mb/google/zork: simplify flashmap file Now that we're using fmaptool to parse the .fmd file, we can use some short forms and omit unnecessary information. BUG=b:157068645 TEST=None BRANCH=zork Change-Id: I81c121d4fce13a9d2aad4477955cb4770794d244 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-22 03:04:20 +02:00
SI_BIOS {
RW_MRC_CACHE 64K
mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-11 04:00:07 +02:00
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
mb/google/zork: Add Picasso based Zork mainboard and variants This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 22:07:41 +02:00
}
mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-11 04:00:07 +02:00
RW_SECTION_B 3M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
mb/google/zork: Add Picasso based Zork mainboard and variants This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 22:07:41 +02:00
}
mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-11 04:00:07 +02:00
RW_ELOG(PRESERVE) 4K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
mb/google/zork: Add Picasso based Zork mainboard and variants This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 22:07:41 +02:00
}
mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-11 04:00:07 +02:00
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 4K
RW_LEGACY(CBFS)
WP_RO@8M 8M {
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
GBB@4K 448K
COREBOOT(CBFS)
mb/google/zork: Add Picasso based Zork mainboard and variants This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20 22:07:41 +02:00
}
}
}
}
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