2016-03-18 00:52:54 +01:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <pci/pci.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <sys/io.h>
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#include <assert.h>
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#include <unistd.h>
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2016-08-26 02:10:51 +02:00
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#include "intelmetool.h"
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2016-03-18 00:52:54 +01:00
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#include "me.h"
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#include "mmap.h"
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#define read32(addr, off) ( *((uint32_t *) (addr + off)) )
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#define write32(addr, off, val) ( *((uint32_t *) (addr + off)) = val)
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/* Path that the BIOS should take based on ME state */
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/*
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static const char *me_bios_path_values[] = {
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[ME_NORMAL_BIOS_PATH] = "Normal",
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[ME_S3WAKE_BIOS_PATH] = "S3 Wake",
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[ME_ERROR_BIOS_PATH] = "Error",
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[ME_RECOVERY_BIOS_PATH] = "Recovery",
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[ME_DISABLE_BIOS_PATH] = "Disable",
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[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
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};
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*/
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/* MMIO base address for MEI interface */
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static uint32_t mei_base_address;
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static uint8_t* mei_mmap;
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static void mei_dump(void *ptr, int dword, int offset, const char *type)
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{
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2017-05-07 08:57:53 +02:00
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/* struct mei_csr *csr; */
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2016-03-18 00:52:54 +01:00
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switch (offset) {
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case MEI_H_CSR:
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case MEI_ME_CSR_HA:
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2017-10-28 18:33:07 +02:00
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/*
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csr = ptr;
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2017-05-07 08:57:53 +02:00
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if (!csr) {
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2016-03-18 00:52:54 +01:00
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printf("%-9s[%02x] : ", type, offset);
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printf("ERROR: 0x%08x\n", dword);
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break;
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}
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printf("%-9s[%02x] : ", type, offset);
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printf("depth=%u read=%02u write=%02u ready=%u "
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2017-10-28 18:33:07 +02:00
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"reset=%u intgen=%u intstatus=%u intenable=%u\n",
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csr->buffer_depth, csr->buffer_read_ptr,
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csr->buffer_write_ptr, csr->ready, csr->reset,
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csr->interrupt_generate, csr->interrupt_status,
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csr->interrupt_enable);
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*/
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break;
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2016-03-18 00:52:54 +01:00
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case MEI_ME_CB_RW:
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case MEI_H_CB_WW:
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printf("%-9s[%02x] : ", type, offset);
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printf("CB: 0x%08x\n", dword);
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break;
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default:
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printf("%-9s[%02x] : ", type, offset);
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printf("0x%08x\n", offset);
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break;
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}
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}
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/*
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* ME/MEI access helpers using memcpy to avoid aliasing.
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*/
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static inline void mei_read_dword_ptr(void *ptr, uint32_t offset)
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{
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uint32_t dword = read32(mei_mmap, offset);
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memcpy(ptr, &dword, sizeof(dword));
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if (debug) {
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mei_dump(ptr, dword, offset, "READ");
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}
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}
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static inline void mei_write_dword_ptr(void *ptr, uint32_t offset)
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{
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uint32_t dword = 0;
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memcpy(&dword, ptr, sizeof(dword));
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write32(mei_mmap, offset, dword);
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if (debug) {
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mei_dump(ptr, dword, offset, "WRITE");
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}
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}
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static inline void pci_read_dword_ptr(struct pci_dev *dev, void *ptr, uint32_t offset)
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{
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uint32_t dword = pci_read_long(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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if (debug) {
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mei_dump(ptr, dword, offset, "PCI READ");
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}
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}
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static inline void read_host_csr(struct mei_csr *csr)
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{
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mei_read_dword_ptr(csr, MEI_H_CSR);
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}
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static inline void write_host_csr(struct mei_csr *csr)
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{
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mei_write_dword_ptr(csr, MEI_H_CSR);
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}
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static inline void read_me_csr(struct mei_csr *csr)
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{
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mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
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}
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static inline void write_cb(uint32_t dword)
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{
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write32(mei_mmap, MEI_H_CB_WW, dword);
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if (debug) {
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mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
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}
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}
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static inline uint32_t read_cb(void)
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{
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uint32_t dword = read32(mei_mmap, MEI_ME_CB_RW);
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if (debug) {
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mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
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}
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return dword;
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}
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/* Wait for ME ready bit to be asserted */
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static int mei_wait_for_me_ready(void)
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{
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struct mei_csr me;
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unsigned try = ME_RETRY;
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while (try--) {
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read_me_csr(&me);
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if (me.ready)
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return 0;
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usleep(ME_DELAY);
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}
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printf("ME: failed to become ready\n");
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return -1;
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}
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void mei_reset(void)
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{
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struct mei_csr host;
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if (mei_wait_for_me_ready() < 0)
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return;
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/* Reset host and ME circular buffers for next message */
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read_host_csr(&host);
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host.reset = 1;
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host.interrupt_generate = 1;
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write_host_csr(&host);
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if (mei_wait_for_me_ready() < 0)
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return;
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/* Re-init and indicate host is ready */
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read_host_csr(&host);
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host.interrupt_generate = 1;
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host.ready = 1;
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host.reset = 0;
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write_host_csr(&host);
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}
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static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
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void *req_data)
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{
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struct mei_csr host;
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unsigned ndata , n;
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uint32_t *data;
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/* Number of dwords to write, ignoring MKHI */
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ndata = (mei->length) >> 2;
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/* Pad non-dword aligned request message length */
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if (mei->length & 3)
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ndata++;
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if (!ndata) {
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printf("ME: request does not include MKHI\n");
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return -1;
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}
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ndata++; /* Add MEI header */
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/*
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* Make sure there is still room left in the circular buffer.
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* Reset the buffer pointers if the requested message will not fit.
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*/
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read_host_csr(&host);
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if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
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printf("ME: circular buffer full, resetting...\n");
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mei_reset();
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read_host_csr(&host);
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}
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/*
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* This implementation does not handle splitting large messages
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* across multiple transactions. Ensure the requested length
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* will fit in the available circular buffer depth.
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*/
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if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
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printf("ME: message (%u) too large for buffer (%u)\n",
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ndata + 2, host.buffer_depth);
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return -1;
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}
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/* Write MEI header */
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mei_write_dword_ptr(mei, MEI_H_CB_WW);
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ndata--;
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/* Write MKHI header */
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mei_write_dword_ptr(mkhi, MEI_H_CB_WW);
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ndata--;
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/* Write message data */
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data = req_data;
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for (n = 0; n < ndata; ++n)
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write_cb(*data++);
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/* Generate interrupt to the ME */
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read_host_csr(&host);
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host.interrupt_generate = 1;
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write_host_csr(&host);
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/* Make sure ME is ready after sending request data */
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return mei_wait_for_me_ready();
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}
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static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
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void *rsp_data, uint32_t rsp_bytes)
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{
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struct mei_header mei_rsp;
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struct mkhi_header mkhi_rsp;
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struct mei_csr me, host;
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unsigned ndata, n;
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unsigned expected;
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uint32_t *data;
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/* Total number of dwords to read from circular buffer */
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expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2;
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if (rsp_bytes & 3)
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expected++;
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if (debug) {
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printf("expected u32 = %d\n", expected);
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}
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/*
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* The interrupt status bit does not appear to indicate that the
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* message has actually been received. Instead we wait until the
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* expected number of dwords are present in the circular buffer.
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*/
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for (n = ME_RETRY; n; --n) {
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read_me_csr(&me);
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if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
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//if (me.interrupt_generate && !me.interrupt_status)
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//if (me.interrupt_status)
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break;
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usleep(ME_DELAY);
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}
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if (!n) {
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printf("ME: timeout waiting for data: expected "
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"%u, available %u\n", expected,
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me.buffer_write_ptr - me.buffer_read_ptr);
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return -1;
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}
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/* Read and verify MEI response header from the ME */
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mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
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if (!mei_rsp.is_complete) {
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printf("ME: response is not complete\n");
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return -1;
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}
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/* Handle non-dword responses and expect at least MKHI header */
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ndata = mei_rsp.length >> 2;
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if (mei_rsp.length & 3)
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ndata++;
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if (ndata != (expected - 1)) { //XXX
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printf("ME: response is missing data\n");
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//return -1;
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}
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/* Read and verify MKHI response header from the ME */
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mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW);
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if (!mkhi_rsp.is_response ||
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mkhi->group_id != mkhi_rsp.group_id ||
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mkhi->command != mkhi_rsp.command) {
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printf("ME: invalid response, group %u ?= %u, "
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"command %u ?= %u, is_response %u\n", mkhi->group_id,
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mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
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mkhi_rsp.is_response);
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//return -1;
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}
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ndata--; /* MKHI header has been read */
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/* Make sure caller passed a buffer with enough space */
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if (ndata != (rsp_bytes >> 2)) {
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printf("ME: not enough room in response buffer: "
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"%u != %u\n", ndata, rsp_bytes >> 2);
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//return -1;
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}
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/* Read response data from the circular buffer */
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data = rsp_data;
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for (n = 0; n < ndata; ++n)
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*data++ = read_cb();
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/* Tell the ME that we have consumed the response */
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read_host_csr(&host);
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host.interrupt_status = 1;
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host.interrupt_generate = 1;
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write_host_csr(&host);
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return mei_wait_for_me_ready();
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}
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static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
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void *req_data, void *rsp_data, uint32_t rsp_bytes)
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{
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if (mei_send_msg(mei, mkhi, req_data) < 0)
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return -1;
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if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0)
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return -1;
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return 0;
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}
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/* Send END OF POST message to the ME */
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/*
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static int mkhi_end_of_post(void)
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{
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struct mkhi_header mkhi = {
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.group_id = MKHI_GROUP_ID_GEN,
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.command = MKHI_END_OF_POST,
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};
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struct mei_header mei = {
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.is_complete = 1,
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.host_address = MEI_HOST_ADDRESS,
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.client_address = MEI_ADDRESS_MKHI,
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.length = sizeof(mkhi),
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};
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|
|
|
|
|
|
|
if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) {
|
|
|
|
printf("ME: END OF POST message failed\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("ME: END OF POST message successful\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Get ME firmware version */
|
2016-08-26 02:10:51 +02:00
|
|
|
int mkhi_get_fw_version(int *major, int *minor)
|
2016-03-18 00:52:54 +01:00
|
|
|
{
|
|
|
|
uint32_t data = 0;
|
|
|
|
struct me_fw_version version = {0};
|
|
|
|
|
|
|
|
struct mkhi_header mkhi = {
|
|
|
|
.group_id = MKHI_GROUP_ID_GEN,
|
|
|
|
.command = GEN_GET_FW_VERSION,
|
|
|
|
.is_response = 0,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct mei_header mei = {
|
|
|
|
.is_complete = 1,
|
|
|
|
.host_address = MEI_HOST_ADDRESS,
|
|
|
|
.client_address = MEI_ADDRESS_MKHI,
|
|
|
|
.length = sizeof(mkhi),
|
|
|
|
};
|
|
|
|
|
|
|
|
#ifndef OLDARC
|
|
|
|
/* Send request and wait for response */
|
|
|
|
if (mei_sendrecv(&mei, &mkhi, &data, &version, sizeof(version) ) < 0) {
|
|
|
|
printf("ME: GET FW VERSION message failed\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
printf("ME: Firmware Version %u.%u.%u.%u (code) "
|
|
|
|
"%u.%u.%u.%u (recovery) "
|
|
|
|
"%u.%u.%u.%u (fitc)\n\n",
|
|
|
|
version.code_major, version.code_minor,
|
|
|
|
version.code_build_number, version.code_hot_fix,
|
|
|
|
version.recovery_major, version.recovery_minor,
|
|
|
|
version.recovery_build_number, version.recovery_hot_fix,
|
|
|
|
version.fitcmajor, version.fitcminor,
|
|
|
|
version.fitcbuildno, version.fitchotfix);
|
|
|
|
#else
|
|
|
|
/* Send request and wait for response */
|
|
|
|
if (mei_sendrecv(&mei, &mkhi, &data, &version, 2*sizeof(uint32_t) ) < 0) {
|
|
|
|
printf("ME: GET FW VERSION message failed\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
printf("ME: Firmware Version %u.%u (code)\n\n"
|
|
|
|
version.code_major, version.code_minor);
|
|
|
|
#endif
|
2016-08-26 02:10:51 +02:00
|
|
|
if (major)
|
|
|
|
*major = version.code_major;
|
|
|
|
if (minor)
|
|
|
|
*minor = version.code_minor;
|
2016-03-18 00:52:54 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get ME Firmware Capabilities */
|
|
|
|
int mkhi_get_fwcaps(void)
|
|
|
|
{
|
|
|
|
struct {
|
|
|
|
uint32_t rule_id;
|
|
|
|
uint32_t rule_len;
|
|
|
|
|
|
|
|
struct me_fwcaps cap;
|
|
|
|
} fwcaps;
|
|
|
|
|
|
|
|
fwcaps.rule_id = 0;
|
|
|
|
fwcaps.rule_len = 0;
|
|
|
|
|
|
|
|
struct mkhi_header mkhi = {
|
|
|
|
.group_id = MKHI_GROUP_ID_FWCAPS,
|
|
|
|
.command = MKHI_FWCAPS_GET_RULE,
|
|
|
|
.is_response = 0,
|
|
|
|
};
|
|
|
|
struct mei_header mei = {
|
|
|
|
.is_complete = 1,
|
|
|
|
.host_address = MEI_HOST_ADDRESS,
|
|
|
|
.client_address = MEI_ADDRESS_MKHI,
|
|
|
|
.length = sizeof(mkhi) + sizeof(fwcaps.rule_id),
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Send request and wait for response */
|
|
|
|
if (mei_sendrecv(&mei, &mkhi, &fwcaps.rule_id, &fwcaps.cap, sizeof(fwcaps.cap)) < 0) {
|
|
|
|
printf("ME: GET FWCAPS message failed\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
print_cap("Full Network manageability ", fwcaps.cap.caps_sku.full_net);
|
|
|
|
print_cap("Regular Network manageability ", fwcaps.cap.caps_sku.std_net);
|
|
|
|
print_cap("Manageability ", fwcaps.cap.caps_sku.manageability);
|
|
|
|
print_cap("Small business technology ", fwcaps.cap.caps_sku.small_business);
|
|
|
|
print_cap("Level III manageability ", fwcaps.cap.caps_sku.l3manageability);
|
|
|
|
print_cap("IntelR Anti-Theft (AT) ", fwcaps.cap.caps_sku.intel_at);
|
2017-10-28 18:33:07 +02:00
|
|
|
print_cap("IntelR Capability Licensing Service (CLS) ", fwcaps.cap.caps_sku.intel_cls);
|
|
|
|
print_cap("IntelR Power Sharing Technology (MPC) ", fwcaps.cap.caps_sku.intel_mpc);
|
2016-03-18 00:52:54 +01:00
|
|
|
print_cap("ICC Over Clocking ", fwcaps.cap.caps_sku.icc_over_clocking);
|
2017-10-28 18:33:07 +02:00
|
|
|
print_cap("Protected Audio Video Path (PAVP) ", fwcaps.cap.caps_sku.pavp);
|
2016-03-18 00:52:54 +01:00
|
|
|
print_cap("IPV6 ", fwcaps.cap.caps_sku.ipv6);
|
|
|
|
print_cap("KVM Remote Control (KVM) ", fwcaps.cap.caps_sku.kvm);
|
|
|
|
print_cap("Outbreak Containment Heuristic (OCH) ", fwcaps.cap.caps_sku.och);
|
|
|
|
print_cap("Virtual LAN (VLAN) ", fwcaps.cap.caps_sku.vlan);
|
|
|
|
print_cap("TLS ", fwcaps.cap.caps_sku.tls);
|
|
|
|
print_cap("Wireless LAN (WLAN) ", fwcaps.cap.caps_sku.wlan);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Tell ME to issue a global reset */
|
|
|
|
uint32_t mkhi_global_reset(void)
|
|
|
|
{
|
|
|
|
struct me_global_reset reset = {
|
|
|
|
.request_origin = GLOBAL_RESET_BIOS_POST,
|
|
|
|
.reset_type = CBM_RR_GLOBAL_RESET,
|
|
|
|
};
|
|
|
|
struct mkhi_header mkhi = {
|
|
|
|
.group_id = MKHI_GROUP_ID_CBM,
|
|
|
|
.command = MKHI_GLOBAL_RESET,
|
|
|
|
};
|
|
|
|
struct mei_header mei = {
|
|
|
|
.is_complete = 1,
|
|
|
|
.length = sizeof(mkhi) + sizeof(reset),
|
|
|
|
.host_address = MEI_HOST_ADDRESS,
|
|
|
|
.client_address = MEI_ADDRESS_MKHI,
|
|
|
|
};
|
|
|
|
|
|
|
|
printf("ME: Requesting global reset\n");
|
|
|
|
|
|
|
|
/* Send request and wait for response */
|
|
|
|
if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
|
|
|
|
/* No response means reset will happen shortly... */
|
|
|
|
asm("hlt");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If the ME responded it rejected the reset request */
|
|
|
|
printf("ME: Global Reset failed\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Tell ME thermal reporting parameters */
|
|
|
|
/*
|
|
|
|
void mkhi_thermal(void)
|
|
|
|
{
|
|
|
|
struct me_thermal_reporting thermal = {
|
|
|
|
.polling_timeout = 2,
|
|
|
|
.smbus_ec_msglen = 1,
|
|
|
|
.smbus_ec_msgpec = 0,
|
|
|
|
.dimmnumber = 4,
|
|
|
|
};
|
|
|
|
struct mkhi_header mkhi = {
|
|
|
|
.group_id = MKHI_GROUP_ID_CBM,
|
|
|
|
.command = MKHI_THERMAL_REPORTING,
|
|
|
|
};
|
|
|
|
struct mei_header mei = {
|
|
|
|
.is_complete = 1,
|
|
|
|
.length = sizeof(mkhi) + sizeof(thermal),
|
|
|
|
.host_address = MEI_HOST_ADDRESS,
|
|
|
|
.client_address = MEI_ADDRESS_THERMAL,
|
|
|
|
};
|
|
|
|
|
|
|
|
printf("ME: Sending thermal reporting params\n");
|
|
|
|
|
|
|
|
mei_sendrecv(&mei, &mkhi, &thermal, NULL, 0);
|
|
|
|
}
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Enable debug of internal ME memory */
|
|
|
|
int mkhi_debug_me_memory(void *physaddr)
|
|
|
|
{
|
|
|
|
uint32_t data = 0;
|
|
|
|
|
|
|
|
/* copy whole ME memory to a readable space */
|
|
|
|
struct me_debug_mem memory = {
|
|
|
|
.debug_phys = (uintptr_t)physaddr,
|
|
|
|
.debug_size = 0x2000000,
|
|
|
|
.me_phys = 0x20000000,
|
|
|
|
.me_size = 0x2000000,
|
|
|
|
};
|
|
|
|
struct mkhi_header mkhi = {
|
|
|
|
.group_id = MKHI_GROUP_ID_GEN,
|
|
|
|
.command = GEN_SET_DEBUG_MEM,
|
|
|
|
.is_response = 0,
|
|
|
|
};
|
|
|
|
struct mei_header mei = {
|
|
|
|
.is_complete = 1,
|
|
|
|
.length = sizeof(mkhi) + sizeof(memory),
|
|
|
|
.host_address = MEI_HOST_ADDRESS,
|
|
|
|
.client_address = MEI_ADDRESS_MKHI,
|
|
|
|
};
|
|
|
|
|
|
|
|
printf("ME: Debug memory to 0x%zx ...", (size_t)physaddr);
|
|
|
|
if (mei_sendrecv(&mei, &mkhi, &memory, &data, 0) < 0) {
|
|
|
|
printf("failed\n");
|
|
|
|
return -1;
|
|
|
|
} else {
|
|
|
|
printf("done\n");
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Prepare ME for MEI messages */
|
|
|
|
uint32_t intel_mei_setup(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct mei_csr host;
|
|
|
|
uint32_t reg32;
|
|
|
|
uint32_t pagerounded;
|
|
|
|
|
|
|
|
mei_base_address = dev->base_addr[0] & ~0xf;
|
|
|
|
pagerounded = mei_base_address & ~0xfff;
|
2017-10-28 18:33:07 +02:00
|
|
|
mei_mmap = map_physical(pagerounded, 0x2000);
|
|
|
|
mei_mmap += mei_base_address - pagerounded;
|
2017-05-04 08:13:38 +02:00
|
|
|
if (mei_mmap == NULL) {
|
2018-02-01 16:12:47 +01:00
|
|
|
printf("Could not map ME setup memory.\n"
|
|
|
|
"Do you have cmdline argument 'iomem=relaxed' set ?\n");
|
2017-05-04 08:13:38 +02:00
|
|
|
return 1;
|
|
|
|
}
|
2016-03-18 00:52:54 +01:00
|
|
|
|
|
|
|
/* Ensure Memory and Bus Master bits are set */
|
|
|
|
reg32 = pci_read_long(dev, PCI_COMMAND);
|
|
|
|
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
|
|
|
pci_write_long(dev, PCI_COMMAND, reg32);
|
|
|
|
|
|
|
|
/* Clean up status for next message */
|
|
|
|
read_host_csr(&host);
|
|
|
|
host.interrupt_generate = 1;
|
|
|
|
host.ready = 1;
|
|
|
|
host.reset = 0;
|
|
|
|
write_host_csr(&host);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read the Extend register hash of ME firmware */
|
|
|
|
int intel_me_extend_valid(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct me_heres status;
|
|
|
|
uint32_t extend[8] = {0};
|
|
|
|
int i, count = 0;
|
|
|
|
|
|
|
|
pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
|
|
|
|
if (!status.extend_feature_present) {
|
|
|
|
printf("ME: Extend Feature not present\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!status.extend_reg_valid) {
|
|
|
|
printf("ME: Extend Register not valid\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (status.extend_reg_algorithm) {
|
|
|
|
case PCI_ME_EXT_SHA1:
|
|
|
|
count = 5;
|
|
|
|
printf("ME: Extend SHA-1: ");
|
|
|
|
break;
|
|
|
|
case PCI_ME_EXT_SHA256:
|
|
|
|
count = 8;
|
|
|
|
printf("ME: Extend SHA-256: ");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("ME: Extend Algorithm %d unknown\n",
|
|
|
|
status.extend_reg_algorithm);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < count; ++i) {
|
|
|
|
extend[i] = pci_read_long(dev, PCI_ME_HER(i));
|
|
|
|
printf("%08x", extend[i]);
|
|
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|