2003-09-02 19:16:48 +02:00
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#include <bitops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/path.h>
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#include <device/pci.h>
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2003-09-04 05:00:54 +02:00
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#include <device/hypertransport.h>
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2003-10-11 08:20:25 +02:00
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#include <device/chip.h>
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2003-09-02 19:16:48 +02:00
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#include <part/hard_reset.h>
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#include <part/fallback_boot.h>
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static device_t ht_scan_get_devs(device_t *old_devices)
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{
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device_t first, last;
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first = *old_devices;
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last = first;
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while(last && last->sibling &&
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2003-10-14 04:36:51 +02:00
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(last->sibling->path.type == DEVICE_PATH_PCI) &&
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2003-09-02 19:16:48 +02:00
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(last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) {
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last = last->sibling;
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}
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if (first) {
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*old_devices = last->sibling;
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last->sibling = 0;
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}
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return first;
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}
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struct prev_link {
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struct device *dev;
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unsigned pos;
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unsigned char config_off, freq_off, freq_cap_off;
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};
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static int ht_setup_link(struct prev_link *prev, device_t dev, unsigned pos)
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{
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static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
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static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
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unsigned present_width_cap, upstream_width_cap;
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unsigned present_freq_cap, upstream_freq_cap;
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unsigned ln_present_width_in, ln_upstream_width_in;
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unsigned ln_present_width_out, ln_upstream_width_out;
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unsigned freq, old_freq;
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unsigned present_width, upstream_width, old_width;
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int reset_needed;
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/* Set the hypertransport link width and frequency */
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reset_needed = 0;
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/* Read the capabilities */
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present_freq_cap = pci_read_config16(dev, pos + PCI_HT_CAP_SLAVE_FREQ_CAP0);
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upstream_freq_cap = pci_read_config16(prev->dev, prev->pos + prev->freq_cap_off);
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present_width_cap = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0);
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upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
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/* Calculate the highest useable frequency */
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#if 0
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freq = log2(present_freq_cap & upstream_freq_cap);
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#else
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/* Errata for 8131 - freq 5 has hardware problems don't support it */
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freq = log2(present_freq_cap & upstream_freq_cap & 0x1f);
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#endif
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/* Calculate the highest width */
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ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
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ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
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if (ln_upstream_width_in > ln_present_width_out) {
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ln_upstream_width_in = ln_present_width_out;
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}
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upstream_width = pow2_to_link_width[ln_upstream_width_in];
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present_width = pow2_to_link_width[ln_upstream_width_in] << 4;
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ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
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ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
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if (ln_upstream_width_out > ln_present_width_in) {
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ln_upstream_width_out = ln_present_width_in;
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}
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upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
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present_width |= pow2_to_link_width[ln_upstream_width_out];
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/* Set the current device */
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old_freq = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_FREQ0);
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if (freq != old_freq) {
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pci_write_config8(dev, pos + PCI_HT_CAP_SLAVE_FREQ0, freq);
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reset_needed = 1;
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printk_spew("HyperT FreqP old %x new %x\n",old_freq,freq);
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}
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old_width = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1);
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if (present_width != old_width) {
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pci_write_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1, present_width);
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reset_needed = 1;
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printk_spew("HyperT widthP old %x new %x\n",old_width, present_width);
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}
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/* Set the upstream device */
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old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
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old_freq &= 0x0f;
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if (freq != old_freq) {
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pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
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reset_needed = 1;
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printk_spew("HyperT freqU old %x new %x\n", old_freq, freq);
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}
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old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
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if (upstream_width != old_width) {
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pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
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reset_needed = 1;
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printk_spew("HyperT widthU old %x new %x\n", old_width, upstream_width);
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}
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/* Remember the current link as the previous link */
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prev->dev = dev;
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prev->pos = pos;
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prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
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prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
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prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
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return reset_needed;
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}
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static unsigned ht_lookup_slave_capability(struct device *dev)
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{
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unsigned pos;
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pos = 0;
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switch(dev->hdr_type & 0x7f) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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pos = PCI_CAPABILITY_LIST;
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break;
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}
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if (pos > PCI_CAP_LIST_NEXT) {
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pos = pci_read_config8(dev, pos);
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}
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while(pos != 0) { /* loop through the linked list */
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uint8_t cap;
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cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
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printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
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if (cap == PCI_CAP_ID_HT) {
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unsigned flags;
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flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
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printk_spew("flags: 0x%04x\n", (unsigned)flags);
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if ((flags >> 13) == 0) {
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/* Entry is a Slave secondary, success...*/
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break;
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}
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}
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if(pos) {
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pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
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}
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}
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return pos;
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}
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static void ht_collapse_early_enumeration(struct bus *bus)
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{
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unsigned int devfn;
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/* Spin through the devices and collapse any early
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* hypertransport enumeration.
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*/
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for(devfn = 0; devfn <= 0xff; devfn += 8) {
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struct device dummy;
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uint32_t id;
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unsigned pos, flags;
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dummy.bus = bus;
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dummy.path.type = DEVICE_PATH_PCI;
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dummy.path.u.pci.devfn = devfn;
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id = pci_read_config32(&dummy, PCI_VENDOR_ID);
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000) {
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continue;
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}
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dummy.vendor = id & 0xffff;
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dummy.device = (id >> 16) & 0xffff;
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dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
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pos = ht_lookup_slave_capability(&dummy);
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if (!pos){
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continue;
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}
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/* Clear the unitid */
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flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
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flags &= ~0x1f;
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pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
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printk_spew("Collapsing %s [%04x/%04x]\n",
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dev_path(&dummy), dummy.vendor, dummy.device);
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}
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}
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unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max)
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{
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unsigned next_unitid, last_unitid, previous_unitid;
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uint8_t previous_pos;
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device_t old_devices, dev, func, *chain_last;
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unsigned min_unitid = 1;
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int reset_needed;
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struct prev_link prev;
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/* Restore the hypertransport chain to it's unitialized state */
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ht_collapse_early_enumeration(bus);
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/* See which static device nodes I have */
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old_devices = bus->children;
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bus->children = 0;
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chain_last = &bus->children;
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/* Initialize the hypertransport enumeration state */
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reset_needed = 0;
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prev.dev = bus->dev;
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prev.pos = bus->cap;
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prev.config_off = PCI_HT_CAP_HOST_WIDTH;
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prev.freq_off = PCI_HT_CAP_HOST_FREQ;
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prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
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/* If present assign unitid to a hypertransport chain */
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last_unitid = min_unitid -1;
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next_unitid = min_unitid;
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previous_pos = 0;
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do {
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uint32_t id, class;
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uint8_t hdr_type, pos;
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uint16_t flags;
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unsigned count, static_count;
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previous_unitid = last_unitid;
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last_unitid = next_unitid;
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/* Get setup the device_structure */
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dev = ht_scan_get_devs(&old_devices);
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if (!dev) {
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struct device dummy;
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dummy.bus = bus;
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dummy.path.type = DEVICE_PATH_PCI;
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dummy.path.u.pci.devfn = 0;
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id = pci_read_config32(&dummy, PCI_VENDOR_ID);
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/* If the chain is fully enumerated quit */
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000) {
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break;
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}
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dev = alloc_dev(bus, &dummy.path);
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}
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else {
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/* Add this device to the pci bus chain */
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*chain_last = dev;
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/* Run the magice enable/disable sequence for the device */
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2003-10-11 08:20:25 +02:00
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if (dev->chip && dev->chip->control && dev->chip->control->enable_dev) {
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dev->chip->control->enable_dev(dev);
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2003-09-02 19:16:48 +02:00
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}
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/* Now read the vendor and device id */
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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2003-10-11 08:20:25 +02:00
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/* If the chain is fully enumerated quit */
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000) {
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printk_err("Missing static device: %s\n",
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dev_path(dev));
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break;
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}
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2003-09-02 19:16:48 +02:00
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}
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/* Update the device chain tail */
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for(func = dev; func; func = func->sibling) {
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chain_last = &func->sibling;
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}
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/* Read the rest of the pci configuration information */
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hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
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class = pci_read_config32(dev, PCI_CLASS_REVISION);
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/* Store the interesting information in the device structure */
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dev->vendor = id & 0xffff;
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dev->device = (id >> 16) & 0xffff;
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dev->hdr_type = hdr_type;
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/* class code, the upper 3 bytes of PCI_CLASS_REVISION */
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dev->class = class >> 8;
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/* Find the hypertransport link capability */
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pos = ht_lookup_slave_capability(dev);
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if (pos == 0) {
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2003-10-11 08:20:25 +02:00
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printk_err("%s Hypertransport link capability not found",
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dev_path(dev));
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2003-09-02 19:16:48 +02:00
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break;
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}
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/* Update the Unitid of the current device */
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flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
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flags &= ~0x1f; /* mask out base Unit ID */
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flags |= next_unitid & 0x1f;
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pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
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/* Update the Unitd id in the device structure */
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static_count = 1;
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for(func = dev; func; func = func->sibling) {
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func->path.u.pci.devfn += (next_unitid << 3);
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static_count = (func->path.u.pci.devfn >> 3)
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- (dev->path.u.pci.devfn >> 3) + 1;
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}
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/* Compute the number of unitids consumed */
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count = (flags >> 5) & 0x1f; /* get unit count */
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printk_spew("%s count: %04x static_count: %04x\n",
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dev_path(dev), count, static_count);
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if (count < static_count) {
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count = static_count;
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}
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/* Update the Unitid of the next device */
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next_unitid += count;
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/* Setup the hypetransport link */
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reset_needed |= ht_setup_link(&prev, dev, pos);
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printk_debug("%s [%04x/%04x] %s next_unitid: %04x\n",
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dev_path(dev),
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dev->vendor, dev->device,
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(dev->enable? "enabled": "disabled"), next_unitid);
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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#if HAVE_HARD_RESET == 1
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if(reset_needed) {
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printk_info("HyperT reset needed\n");
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2004-02-09 23:47:38 +01:00
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// By LYH hard_reset();
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} else
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2003-09-02 19:16:48 +02:00
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printk_debug("HyperT reset not needed\n");
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#endif
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if (next_unitid > 0x1f) {
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next_unitid = 0x1f;
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}
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return pci_scan_bus(bus, 0x00, (next_unitid << 3)|7, max);
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}
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