2010-07-16 22:02:09 +02:00
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/*
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ETHERBOOT - BOOTP/TFTP Bootstrap Program
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Author: Martin Renters
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Date: May/94
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This code is based heavily on David Greenman's if_ed.c driver
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Copyright (C) 1993-1994, David Greenman, Martin Renters.
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This software may be used, modified, copied, distributed, and sold, in
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both source and binary form provided that the above copyright and these
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terms are retained. Under no circumstances are the authors responsible for
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the proper functioning of this software, nor do the authors assume any
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responsibility for damages incurred with its use.
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Multicast support added by Timothy Legge (timlegge@users.sourceforge.net) 09/28/2003
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Relocation support added by Ken Yap (ken_yap@users.sourceforge.net) 28/12/02
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3c503 support added by Bill Paul (wpaul@ctr.columbia.edu) on 11/15/94
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SMC8416 support added by Bill Paul (wpaul@ctr.columbia.edu) on 12/25/94
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3c503 PIO support added by Jim Hague (jim.hague@acm.org) on 2/17/98
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RX overrun by Klaus Espenlaub (espenlaub@informatik.uni-ulm.de) on 3/10/99
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parts taken from the Linux 8390 driver (by Donald Becker and Paul Gortmaker)
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SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02
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based on the Linux 8390 driver (by Donald Becker and Paul Gortmaker)
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(C) Rudolf Marek <r.marek@assembler.cz> Simplify for RTL8029, Add coreboot glue logic
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*/
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#define ETH_ALEN 6 /* Size of Ethernet address */
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#define ETH_HLEN 14 /* Size of ethernet header */
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#define ETH_ZLEN 60 /* Minimum packet */
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#define ETH_FRAME_LEN 1514 /* Maximum packet */
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#define ETH_DATA_ALIGN 2 /* Amount needed to align the data after an ethernet header */
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#define ETH_MAX_MTU (ETH_FRAME_LEN-ETH_HLEN)
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#include "ns8390.h"
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#include <ip_checksum.h>
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#include <console/ne2k.h>
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#include <arch/io.h>
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//#include <arch/romcc_io.h>
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#define MEM_SIZE MEM_32768
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#define TX_START 64
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#define RX_START (64 + D8390_TXBUF_SIZE)
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static unsigned int get_count(unsigned int eth_nic_base)
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{
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unsigned int ret;
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outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1,
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eth_nic_base + D8390_P0_COMMAND);
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ret = inb(eth_nic_base + 8 + 0) | (inb(eth_nic_base + 8 + 1) << 8);
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outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0,
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eth_nic_base + D8390_P0_COMMAND);
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return ret;
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}
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static void set_count(unsigned int eth_nic_base, unsigned int what)
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{
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outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1,
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eth_nic_base + D8390_P0_COMMAND);
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outb(what & 0xff,eth_nic_base + 8);
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outb((what >> 8) & 0xff,eth_nic_base + 8 + 1);
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outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0,
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eth_nic_base + D8390_P0_COMMAND);
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}
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static void eth_pio_write(unsigned char *src, unsigned int dst, unsigned int cnt,
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unsigned int eth_nic_base)
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{
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outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
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outb(cnt, eth_nic_base + D8390_P0_RBCR0);
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outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1);
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outb(dst, eth_nic_base + D8390_P0_RSAR0);
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outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1);
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outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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while (cnt--) {
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outb(*(src++), eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
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}
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/*
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#warning "Add timeout"
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*/
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/* wait for operation finish */
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while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC)
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;
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}
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void ne2k_append_data(unsigned char *d, int len, unsigned int base)
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{
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eth_pio_write(d, (TX_START << 8) + 42 + get_count(base), len, base);
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set_count(base, get_count(base)+len);
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}
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#ifdef __ROMCC__
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void eth_pio_write_byte(int data, unsigned short dst, unsigned int eth_nic_base)
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{
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outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
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outb(1, eth_nic_base + D8390_P0_RBCR0);
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outb(0, eth_nic_base + D8390_P0_RBCR1);
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outb(dst, eth_nic_base + D8390_P0_RSAR0);
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outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1);
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outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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outb(data, eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
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while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC) != D8390_ISR_RDC)
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;
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}
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void ne2k_append_data_byte(int d, unsigned int base)
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{
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eth_pio_write_byte(d, (TX_START << 8) + 42 + get_count(base), base);
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set_count(base, get_count(base)+1);
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}
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static unsigned char eth_pio_read_byte(unsigned int src,
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unsigned int eth_nic_base)
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{
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outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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outb(0, eth_nic_base + D8390_P0_RBCR0);
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outb(1, eth_nic_base + D8390_P0_RBCR1);
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outb(src, eth_nic_base + D8390_P0_RSAR0);
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outb(src >> 8, eth_nic_base + D8390_P0_RSAR1);
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outb(D8390_COMMAND_RD0 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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return inb(eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
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}
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/* varition of compute_ip_checksum which works on SRAM */
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unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned short length,
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unsigned int eth_nic_base)
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{
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unsigned long sum;
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unsigned long i;
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/* In the most straight forward way possible,
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* compute an ip style checksum.
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*/
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sum = 0;
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for(i = 0; i < length; i++) {
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unsigned long v;
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v = eth_pio_read_byte((TX_START << 8)+i+offset, eth_nic_base);
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if (i & 1) {
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v <<= 8;
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}
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/* Add the new value */
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sum += v;
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/* Wrap around the carry */
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if (sum > 0xFFFF) {
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sum = (sum + (sum >> 16)) & 0xFFFF;
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}
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}
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return (~((sum & 0xff) | (((sum >> 8) & 0xff) << 8) )) & 0xffff;
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}
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static void str2ip_load(const char *str, unsigned short offset, unsigned int eth_nic_base)
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#else
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static void str2ip(const char *str, unsigned char *ip)
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#endif
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{
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unsigned char c, i = 0;
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int acc = 0;
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do {
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c = str[i];
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if ((c >= '0') && (c <= '9')) {
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acc *= 10;
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acc += (c - '0');
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} else {
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#ifdef __ROMCC__
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eth_pio_write_byte(acc, (TX_START << 8)+offset, eth_nic_base);
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offset++;
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#else
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*ip++ = acc;
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#endif
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acc = 0;
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}
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i++;
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} while (c != '\0');
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}
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#ifdef __ROMCC__
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static void str2mac_load(const char *str, unsigned short offset, unsigned int eth_nic_base)
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#else
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static void str2mac(const char *str, unsigned char *mac)
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#endif
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{
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unsigned char c, i = 0;
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int acc = 0;
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do {
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c = str[i];
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if ((c >= '0') && (c <= '9')) {
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acc *= 16;
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acc += (c - '0');
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} else if ((c >= 'a') && (c <= 'f')) {
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acc *= 16;
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acc += ((c - 'a') + 10) ;
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} else if ((c >= 'A') && (c <= 'F')) {
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acc *= 16;
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acc += ((c - 'A') + 10) ;
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} else {
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#ifdef __ROMCC__
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eth_pio_write_byte(acc, ((TX_START << 8)+offset), eth_nic_base);
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offset++;
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#else
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*mac++ = acc;
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#endif
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acc = 0;
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}
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i++;
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} while (c != '\0');
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}
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#ifndef __ROMCC__
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static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) {
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unsigned short chksum;
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unsigned char hdr[] = {
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#else
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static const unsigned char hdr[] = {
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#endif
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/*
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* ETHERNET HDR
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*/
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// destination macaddr
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0x02, 0x00, 0x00, 0x00, 0x00, 0x01,
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/* source mac */
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0x02, 0x00, 0x00, 0xC0, 0xFF, 0xEE,
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/* ethtype (IP) */
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0x08, 0x00,
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/*
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* IP HDR
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*/
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0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00,
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/* TTL, proto (UDP), chksum_hi, chksum_lo, IP0, IP1, IP2, IP3, */
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0x40, 0x11, 0x0, 0x0, 0x7f, 0x0, 0x0, 0x1,
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/* IP0, IP1, IP2, IP3 */
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0xff, 0xff, 0xff, 0xff,
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/*
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* UDP HDR
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*/
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/* SRC PORT DST PORT (2bytes each), ulen, uchksum (must be zero or correct */
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0x1a, 0x0b, 0x1a, 0x0a, 0x00, 0x9, 0x00, 0x00,
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};
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#ifndef __ROMCC__
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str2mac(CONFIG_CONSOLE_NE2K_DST_MAC, &hdr[0]);
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str2ip(CONFIG_CONSOLE_NE2K_DST_IP, &hdr[30]);
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str2ip(CONFIG_CONSOLE_NE2K_SRC_IP, &hdr[26]);
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/* zero checksum */
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hdr[24] = 0;
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hdr[25] = 0;
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/* update IP packet len */
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hdr[16] = ((28 + pktlen) >> 8) & 0xff;
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hdr[17] = (28 + pktlen) & 0xff;
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/* update UDP len */
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hdr[38] = (8 + pktlen) >> 8;
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hdr[39] = 8 + pktlen;
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chksum = compute_ip_checksum(&hdr[14], 20);
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hdr[25] = chksum >> 8;
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hdr[24] = chksum;
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eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base);
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}
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#else
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/* ROMCC madness */
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static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen)
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{
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unsigned short chksum;
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eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base);
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str2mac_load(CONFIG_CONSOLE_NE2K_DST_MAC, 0, eth_nic_base);
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str2ip_load(CONFIG_CONSOLE_NE2K_DST_IP, 30, eth_nic_base);
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str2ip_load(CONFIG_CONSOLE_NE2K_SRC_IP, 26, eth_nic_base);
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/* zero checksum */
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eth_pio_write_byte(0, (TX_START << 8)+24, eth_nic_base);
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eth_pio_write_byte(0, (TX_START << 8)+25, eth_nic_base);
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/* update IP packet len */
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eth_pio_write_byte(((28 + pktlen) >> 8) & 0xff, (TX_START << 8)+16, eth_nic_base);
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eth_pio_write_byte( (28 + pktlen) & 0xff, (TX_START << 8)+17, eth_nic_base);
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/* update UDP len */
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eth_pio_write_byte((8 + pktlen) >> 8, (TX_START << 8)+38, eth_nic_base);
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eth_pio_write_byte( 8 + pktlen, (TX_START << 8)+39, eth_nic_base);
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chksum = compute_ip_checksum_from_sram(14, 20, eth_nic_base);
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eth_pio_write_byte(chksum, (TX_START << 8)+24, eth_nic_base);
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eth_pio_write_byte(chksum >> 8, (TX_START << 8)+25, eth_nic_base);
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}
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#endif
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void ne2k_transmit(unsigned int eth_nic_base) {
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unsigned int pktsize;
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unsigned int len = get_count(eth_nic_base);
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// so place whole header inside chip buffer
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ns8390_tx_header(eth_nic_base, len);
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// commit sending now
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outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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outb(TX_START, eth_nic_base + D8390_P0_TPSR);
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pktsize = 42 + len;
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if (pktsize < 64)
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pktsize = 64;
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outb(pktsize, eth_nic_base + D8390_P0_TBCR0);
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outb(pktsize >> 8, eth_nic_base + D8390_P0_TBCR1);
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outb(D8390_ISR_PTX, eth_nic_base + D8390_P0_ISR);
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outb(D8390_COMMAND_PS0 | D8390_COMMAND_TXP | D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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|
|
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|
|
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/* wait for operation finish */
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|
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while ((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_PTX) != D8390_ISR_PTX) ;
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|
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set_count(eth_nic_base, 0);
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|
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}
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|
#ifdef __PRE_RAM__
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#include <arch/romcc_io.h>
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|
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static void ns8390_reset(unsigned int eth_nic_base)
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|
|
|
{
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int i;
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outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
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D8390_COMMAND_STP, eth_nic_base + D8390_P0_COMMAND);
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|
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outb(0x48, eth_nic_base + D8390_P0_DCR);
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outb(0, eth_nic_base + D8390_P0_RBCR0);
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|
outb(0, eth_nic_base + D8390_P0_RBCR1);
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outb(0x20, eth_nic_base + D8390_P0_RCR);
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|
outb(2, eth_nic_base + D8390_P0_TCR);
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outb(TX_START, eth_nic_base + D8390_P0_TPSR);
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|
|
outb(RX_START, eth_nic_base + D8390_P0_PSTART);
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|
|
|
outb(MEM_SIZE, eth_nic_base + D8390_P0_PSTOP);
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|
|
|
outb(MEM_SIZE - 1, eth_nic_base + D8390_P0_BOUND);
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|
|
|
outb(0xFF, eth_nic_base + D8390_P0_ISR);
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|
|
|
outb(0, eth_nic_base + D8390_P0_IMR);
|
|
|
|
|
|
|
|
outb(D8390_COMMAND_PS1 |
|
|
|
|
D8390_COMMAND_RD2 | D8390_COMMAND_STP,
|
|
|
|
eth_nic_base + D8390_P0_COMMAND);
|
|
|
|
|
|
|
|
for (i = 0; i < ETH_ALEN; i++)
|
|
|
|
outb(0x0C, eth_nic_base + D8390_P1_PAR0 + i);
|
|
|
|
|
|
|
|
for (i = 0; i < ETH_ALEN; i++)
|
|
|
|
outb(0xFF, eth_nic_base + D8390_P1_MAR0 + i);
|
|
|
|
|
|
|
|
outb(RX_START, eth_nic_base + D8390_P1_CURR);
|
|
|
|
outb(D8390_COMMAND_PS0 |
|
|
|
|
D8390_COMMAND_RD2 | D8390_COMMAND_STA,
|
|
|
|
eth_nic_base + D8390_P0_COMMAND);
|
|
|
|
outb(0xFF, eth_nic_base + D8390_P0_ISR);
|
|
|
|
outb(0, eth_nic_base + D8390_P0_TCR);
|
|
|
|
outb(4, eth_nic_base + D8390_P0_RCR);
|
|
|
|
set_count(eth_nic_base, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int ne2k_init(unsigned int eth_nic_base) {
|
|
|
|
|
|
|
|
device_t dev;
|
|
|
|
unsigned char c;
|
|
|
|
|
|
|
|
/* Power management controller */
|
|
|
|
dev = pci_locate_device(PCI_ID(0x10ec,
|
|
|
|
0x8029), 0);
|
|
|
|
|
|
|
|
if (dev == PCI_DEV_INVALID)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pci_write_config32(dev, 0x10, eth_nic_base | 1 );
|
|
|
|
pci_write_config8(dev, 0x4, 0x1);
|
|
|
|
|
|
|
|
c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET);
|
|
|
|
outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET);
|
|
|
|
|
|
|
|
(void) inb(0x84);
|
|
|
|
|
|
|
|
outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND);
|
|
|
|
outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR);
|
|
|
|
|
|
|
|
outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
|
|
|
|
outb(MEM_8192, eth_nic_base + D8390_P0_PSTART);
|
|
|
|
outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP);
|
|
|
|
|
|
|
|
ns8390_reset(eth_nic_base);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
#include <delay.h>
|
|
|
|
#include <stdlib.h>
|
|
|
|
#include <string.h>
|
|
|
|
#include <arch/io.h>
|
|
|
|
|
|
|
|
#include <console/console.h>
|
|
|
|
#include <device/device.h>
|
|
|
|
#include <device/pci.h>
|
|
|
|
#include <device/pci_ids.h>
|
|
|
|
#include <device/pci_ops.h>
|
|
|
|
|
|
|
|
static void read_resources(struct device *dev)
|
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
res = new_resource(dev, PCI_BASE_ADDRESS_0);
|
|
|
|
res->base = CONFIG_CONSOLE_NE2K_IO_PORT;
|
|
|
|
res->size = 32;
|
|
|
|
res->align = 5;
|
|
|
|
res->gran = 5;
|
|
|
|
res->limit = res->base + res->size - 1;
|
|
|
|
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_STORED |
|
|
|
|
IORESOURCE_ASSIGNED;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-04-18 04:26:56 +02:00
|
|
|
static struct device_operations ne2k_ops = {
|
2010-07-16 22:02:09 +02:00
|
|
|
.read_resources = read_resources,
|
|
|
|
.set_resources = pci_dev_set_resources,
|
|
|
|
.enable_resources = pci_dev_enable_resources,
|
|
|
|
.init = 0,
|
|
|
|
.scan_bus = 0,
|
|
|
|
};
|
|
|
|
|
2011-04-18 04:26:56 +02:00
|
|
|
static const struct pci_driver ne2k_driver __pci_driver = {
|
2010-07-16 22:02:09 +02:00
|
|
|
.ops = &si_sata_ops,
|
|
|
|
.vendor = 0x10ec,
|
|
|
|
.device = 0x8029,
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif
|