313 lines
9.5 KiB
Text
313 lines
9.5 KiB
Text
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FAILOVER_IMAGE
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default ROM_SECTION_SIZE = FAILOVER_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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end
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 65536
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if USE_FAILOVER_IMAGE
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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else
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if USE_FALLBACK_IMAGE
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
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else
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default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
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end
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end
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arch i386 end
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driver mainboard.o
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object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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# object reset.o
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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else
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makerule ./cache_as_ram_auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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end
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if USE_FAILOVER_IMAGE
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else
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if CONFIG_AP_CODE_IN_CAR
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makerule ./apc_auto.o
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depends "$(MAINBOARD)/apc_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
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end
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ldscript /arch/i386/init/ldscript_apc.lb
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end
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end
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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end
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mainboardinit southbridge/nvidia/mcp55/id.inc
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ldscript /southbridge/nvidia/mcp55/id.lds
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# ROMSTRAP table for MCP55.
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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else
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if USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/mcp55/romstrap.inc
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ldscript /southbridge/nvidia/mcp55/romstrap.lds
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end
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end
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if USE_DCACHE_RAM
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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if HAVE_FAILOVER_BOOT
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if USE_FAILOVER_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover_failover.lds
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end
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end
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else
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if USE_FALLBACK_IMAGE
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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end
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end
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end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject cache_as_ram_auto.o
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else
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mainboardinit ./cache_as_ram_auto.inc
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end
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end
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if CONFIG_CHIP_NAME
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config chip.h
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end
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chip northbridge/amd/amdk8/root_complex # Root complex
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device apic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_AM2 # CPU
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # Northbridge / mc0
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device pci 18.0 on
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/mcp55 # Southbridge
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/winbond/w83627ehg # Super I/O
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device pnp 4e.5 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.6 off # Com2 / IrDA
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 4e.7 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.8 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 4e.b on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 4e.c on # PS/2 mouse
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irq 0x70 = 12
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end
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end
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic # DIMM 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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# TODO: Needed?
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# chip drivers/generic/generic # DIMM 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic # DIMM 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic # DIMM 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic # DIMM 1-1-1
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# device i2c 57 on end
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# end
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end
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# TODO: Check if the stuff below is correct / needed.
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device pci 1.1 on # SM 1
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# PCI device SMBus address will depend on addon PCI device,
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# do we need to scan_smbus_bus?
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# chip drivers/generic/generic # PCIXA Slot1
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic # PCIXB Slot1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic # PCIXB Slot2
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic # PCI Slot1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic # Master MCP55 PCI-E
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic # Slave MCP55 PCI-E
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# device i2c 55 on end
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# end
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chip drivers/generic/generic # MAC EEPROM
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device i2c 51 on end
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end
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end
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 on end # IDE
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device pci 5.0 on end # SATA 0
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device pci 5.1 on end # SATA 1
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device pci 5.2 off end # SATA 2 (N/A on this board)
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device pci 6.0 on end # PCI
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device pci 6.1 on end # AZA (HD Audio)
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device pci 8.0 on end # NIC
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device pci 9.0 off end # NIC (N/A on this board)
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device pci a.0 off end # PCI E 5 (N/A on this board?)
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device pci b.0 on end # PCI E 4
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device pci c.0 on end # PCI E 3
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device pci d.0 on end # PCI E 2
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device pci e.0 on end # PCI E 1
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device pci f.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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# TODO: Check the two lines below.
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register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
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register "mac_eeprom_addr" = "0x51"
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end
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end
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device pci 18.0 on end # Link 1
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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# TODO
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 on end # pci_regs_all
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# device pnp 0.2 on end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 on end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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# device pnp 0.8 off end # io
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# device pnp 0.9 off end # io
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# end
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end
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