91 lines
2.7 KiB
C
91 lines
2.7 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/i2c.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/nvidia/tegra132/clk_rst.h>
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#include <soc/nvidia/tegra132/gpio.h>
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#include <soc/nvidia/tegra132/pinmux.h>
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#include <soc/nvidia/tegra132/spi.h> /* FIXME: move back to soc code? */
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#include "pmic.h"
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static void set_clock_sources(void)
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{
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/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
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writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
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clock_configure_source(mselect, PLLP, 102000);
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/* The PMIC is on I2C5 and can run at 400 KHz. */
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clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
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/* TODO: We should be able to set this to 50MHz, but that did not seem
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* reliable. */
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clock_configure_source(sbc4, PLLP, 33333);
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}
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void bootblock_mainboard_init(void)
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{
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set_clock_sources();
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clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
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CLK_H_I2C5 | CLK_H_APBDMA,
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0, CLK_V_MSELECT, 0, 0);
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// Board ID GPIOs, bits 0-3.
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gpio_input(GPIO(Q3));
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gpio_input(GPIO(T1));
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gpio_input(GPIO(X1));
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gpio_input(GPIO(X4));
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// I2C5 (PMU) clock.
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pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
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PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
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// I2C5 (PMU) data.
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pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
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PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
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i2c_init(4);
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pmic_init(4);
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/* SPI4 data out (MOSI) */
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pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
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PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
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PINMUX_PULL_UP);
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/* SPI4 data in (MISO) */
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pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
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PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
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PINMUX_PULL_UP);
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/* SPI4 clock */
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pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
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PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
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/* SPI4 chip select 0 */
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pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
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PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
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tegra_spi_init(4);
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}
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