93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <lib.h>
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#include <stdlib.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <device/device.h>
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#include <soc/nvidia/tegra/types.h>
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#include <soc/display.h>
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#include <soc/mipi_dsi.h>
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#include <soc/mipi_display.h>
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#include <soc/tegra_dsi.h>
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#include <soc/mipi-phy.h>
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int mipi_dphy_set_timing(struct tegra_dsi *dsi)
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{
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u32 freq = (dsi->clk_rate * 2) / 1000000;
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u32 thsdexit = (DSI_PHY_TIMING_DIV(120, (freq)));
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u32 thstrial = (((3) + (DSI_PHY_TIMING_DIV((DSI_THSTRAIL_VAL(freq)),
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freq))));
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u32 tdatzero = DSI_PHY_TIMING_DIV(((145) + (5 * (DSI_TBIT(freq)))),
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(freq));
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u32 thsprepare = DSI_PHY_TIMING_DIV((65 + (5*(DSI_TBIT(freq)))), freq);
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u32 tclktrial = (DSI_PHY_TIMING_DIV(80, freq));
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u32 tclkpost = ((DSI_PHY_TIMING_DIV(((70) + ((52) * (DSI_TBIT(freq)))),
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freq)));
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u32 tclkzero = (DSI_PHY_TIMING_DIV(260, freq));
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u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq)) ;
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u32 tclkprepare = (DSI_PHY_TIMING_DIV(60, freq));
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u32 tclkpre = 1; //min = 8*UI per mipi spec, tclk_pre=0 should be ok, but using 1 value
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u32 twakeup = 0x7F; //min = 1ms
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u32 ttaget;
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u32 ttassure;
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u32 ttago;
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u32 value;
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if (!ttlpx) {
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ttaget = 5;
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ttassure = 2;
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ttago = 4;
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} else {
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ttaget = 5 * ttlpx;
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ttassure = 2 * ttlpx;
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ttago = 4 * ttlpx;
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}
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value = (thsdexit << 24) |
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(thstrial << 16) |
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(tdatzero << 8) |
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(thsprepare << 0);
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tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
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value = (tclktrial << 24) |
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(tclkpost << 16) |
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(tclkzero << 8) |
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(ttlpx << 0);
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tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
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value = (tclkprepare << 16) |
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(tclkpre << 8) |
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(twakeup << 0);
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tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
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value = (ttaget << 16) |
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(ttassure << 8) |
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(ttago << 0),
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tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
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return 0;
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}
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