113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/i8259.h>
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#include <stdlib.h>
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static const unsigned char enetIrqs[4] = { 10, 0, 0, 0 };
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static const unsigned char usbIrqs[4] = { 15, 14, 0, 0 };
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static void pci_routing_fixup(struct device *dev)
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{
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pci_assign_irqs(0, 0x8, enetIrqs);
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pci_assign_irqs(0, 0xa, usbIrqs);
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}
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static void r8610_init(struct device *dev)
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{
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device_t nb_dev;
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u32 tmp;
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printk(BIOS_DEBUG, "r8610 init\n");
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/* clear DMA? */
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outb(0x4, 0x8);
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outb(0x4, 0x10);
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outb(0xfc, 0x61);
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/* Set serial base */
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pci_write_config32(dev, 0x54, 0x3f8);
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/* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
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pci_write_config32(dev, 0x50, 0x84101012);
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/* Enable internal Port92, enable chipselect for flash */
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tmp = pci_read_config32(dev, 0x40);
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pci_write_config32(dev, 0x40, tmp | 0x07FF0600);
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/* buffer strength SB pins */
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pci_write_config32(dev, 0x5c, 0x2315);
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/* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9, INTC 9, INTB 12, INTA INT10 */
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pci_write_config32(dev, 0x58, 0xdf0311b3);
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/* USB PHY control */
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nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
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PCI_DEVICE_ID_RDC_R8610_NB, 0);
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tmp = pci_read_config32(nb_dev, 0xc0);
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tmp |= 0x40000;
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pci_write_config32(nb_dev, 0xc0, tmp);
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setup_i8259();
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}
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static void r8610_read_resources(device_t dev)
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{
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struct resource *res;
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pci_dev_read_resources(dev);
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res = new_resource(dev, 1);
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res->base = 0x0UL;
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res->size = 0x1000UL;
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res->limit = 0xffffUL;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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/* Reserve space for flash */
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res = new_resource(dev, 2);
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res->base = 0xff800000;
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res->size = 8*1024*1024;
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res->limit = 0xffffffffUL;
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res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
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IORESOURCE_ASSIGNED;
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}
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static void southbridge_init(struct device *dev)
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{
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r8610_init(dev);
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pci_routing_fixup(dev);
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}
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static struct device_operations r8610_sb_ops = {
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.read_resources = r8610_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = &southbridge_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static const struct pci_driver lpc_driver __pci_driver = {
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.ops = &r8610_sb_ops,
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.vendor = PCI_VENDOR_ID_RDC,
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.device = PCI_DEVICE_ID_RDC_R8610_SB,
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};
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