42 lines
1.6 KiB
Markdown
42 lines
1.6 KiB
Markdown
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# Blobs used in Intel Broadwell boards
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All Broadwell boards supported by coreboot require two proprietary blobs.
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In a coreboot image of a Broadwell board, the blobs are named `mrc.bin` and
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`refcode` in CBFS.
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`mrc.bin` is run in romstage to initialize the memory. It is placed at a fixed
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address in CBFS and is loaded at a fixed address in memory.
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`refcode` is run in ramstage to initialize the system agent and the PCH. It is
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a relocatable ELF object.
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## Obtaining the blobs
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Both `mrc.bin` and `refcode` can be obtained from a coreboot image of a Broadwell
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board, for example a Purism Librem 13 v1 coreboot image from [MrChromebox].
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cbfstool coreboot_*.rom extract -f broadwell-mrc.bin -n mrc.bin
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cbfstool coreboot_*.rom extract -m x86 -f broadwell-refcode.elf -n fallback/refcode
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## SPD Addresses
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The SPD addresses in Broadwell `pei_data` struct are similar to [Haswell].
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## Intel GbE support
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Unlike Haswell boards, the `pei_data` struct of Broadwell doesn't have `gbe_enable`
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field. For boards with an Intel GbE device, a modification of `refcode` is needed,
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otherwise `refcode` will disable the Intel GbE device and the OS cannot find it
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in the list of PCI devices.
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## Use Broadwell SoC code for Haswell ULT boards
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Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT
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boards, `devicetree.cb` file and `pei_data` code need to be ported to Broadwell, and
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build the code with Broadwell `mrc.bin` and `refcode` instead of using Haswell `mrc.bin`.
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Broadwell SoC code doesn't support non-ULT Haswell or non-ULT Broadwell boards.
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[MrChromebox]: https://mrchromebox.tech/
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[Haswell]: ../../../northbridge/intel/haswell/mrc.bin.md
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