107 lines
3.7 KiB
Markdown
107 lines
3.7 KiB
Markdown
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# ASUS P3B-F
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This page describes how to run coreboot on the ASUS P3B-F mainboard.
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## Flashing coreboot
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```eval_rst
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+---------------------+---------------------------+
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| Type | Value |
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+=====================+===========================+
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| Model | SST 39SF020A (or similar) |
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+---------------------+---------------------------+
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| Protocol | Parallel |
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+---------------------+---------------------------+
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| Size | 256 KiB |
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+---------------------+---------------------------+
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| Package | DIP-32 |
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+---------------------+---------------------------+
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| Socketed | yes |
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+---------------------+---------------------------+
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| Write protection | See below |
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+---------------------+---------------------------+
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| Internal flashing | yes |
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+---------------------+---------------------------+
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```
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flashrom supports this mainboard since commit c7e9a6e15153684672bbadd1fc6baed8247ba0f6.
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If you are using older versions of flashrom, below has to be done (with ACPI disabled!)
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before flashrom can detect the flash chip:
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```bash
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# rmmod w83781d
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# modprobe i2c-dev
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# i2cset 0 0x48 0x80 0x80
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```
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Upon power up, flash chip is inaccessible until flashrom has been run once.
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Since flashrom does not support reversing board enabling steps,
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once it detects the flash chip, there will be no write protection until
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the next power cycle.
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### CPU microcode considerations
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By default, this board includes microcode updates for 5 families of Intel CPUs
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because of the wide variety of CPUs the board supports, directly or with an
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adapter. These take up a third of the total flash space leaving only 20kB free
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in the final cbfs image. It may be necessary to build a custom microcode update
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file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
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for only CPU models that the board will actually be run with.
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## Working
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- Slot 1 and Socket 370 CPUs and their L1/L2 caches
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- PS/2 keyboard with SeaBIOS (See [Known issues])
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- IDE hard drives
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- USB
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- PCI add-on cards
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- AGP graphics cards
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- Serial ports 1 and 2
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- Reboot
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## Known issues
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- PS/2 keyboard may not be usable until Linux has completely booted. With SeaBIOS
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as payload, setting keyboard initialization timeout to 2500ms may help.
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- The coreboot+SeaBIOS combination boots so quickly some IDE hard drives are not
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yet ready by the time SeaBIOS attempts to boot from them.
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- i440BX does not support 256Mbit RAM modules. If installed, coreboot
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will attempt to initialize them at half their capacity anyway
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whereas vendor firmware will not boot at all.
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- ECC memory can be used, but ECC support is still pending.
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## Untested
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- Floppy
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- Parallel port
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- EDO memory
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- ECC memory
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- Infrared
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- PC speaker
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## Not working
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- ACPI (Support is currently [under gerrit review](https://review.coreboot.org/c/coreboot/+/41098))
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/i440bx/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | i82371eb |
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+------------------+--------------------------------------------------+
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| CPU | P6 family for Slot 1 and Socket 370 |
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| | (all models from model_63x to model_6bx) |
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+------------------+--------------------------------------------------+
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| Super I/O | winbond/w83977tf |
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+------------------+--------------------------------------------------+
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```
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## Extra resources
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[flashrom]: https://flashrom.org/Flashrom
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