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soc/intel/jasperlake: Use coreboot lock down config 

Allow lockdown configuration from using CHIPSET_LOCKDOWN_COREBOOT
config.

TEST=Build and boot waddledoo board

Change-Id: I3abaa737580ef45b98cabfa23edd84162037dd70
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2020-05-19 20:11:13 +05:30 committed by Furquan Shaikh
parent e3f564988b
commit 0018d0f0de
1 changed files with 13 additions and 2 deletions
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13
src/soc/intel/jasperlake/fsp_params.c
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@ -7,6 +7,7 @@
#include <intelblocks/lpss.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@ -105,8 +106,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
}
/* Unlock upper 8 bytes of RTC RAM */
/* Chipset Lockdown */
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
params->PchLockDownGlobalSmi = 0;
params->PchLockDownBiosInterface = 0;
params->PchUnlockGpioPads = 1;
params->RtcMemoryLock = 0;
} else {
params->PchLockDownGlobalSmi = 1;
params->PchLockDownBiosInterface = 1;
params->PchUnlockGpioPads = 0;
params->RtcMemoryLock = 1;
}
/* Enable End of Post in PEI phase */
params->EndOfPostMessage = EOP_PEI;