cpu/intel/model_fxx: Select SSE2

Starting from Intel Pentium 4, cpus featured SSE2.
This will be used in the follow-up patches to determine whether to use
mfence as this instruction was introduced with the SSE2 feature set.

Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2022-05-25 14:51:50 +02:00 committed by Paul Fagerburg
parent 346db92f8c
commit 0024678d17
3 changed files with 3 additions and 0 deletions

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@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_F2X
select SUPPORT_CPU_UCODE_IN_CBFS
select SMM_ASEG
select CPU_INTEL_COMMON
select SSE2

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@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_F3X
select ARCH_X86
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select SSE2

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@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_F4X
bool
select ARCH_X86
select SUPPORT_CPU_UCODE_IN_CBFS
select SSE2