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soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay setting 

MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which
is different from previous SoCs, so we define a macro to get the
designated register.

TEST=build pass.
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Rex-BC Chen 2022-07-27 16:12:12 +08:00 committed by Paul Fagerburg
parent d699de071f
commit 00324b20e1
6 changed files with 13 additions and 8 deletions
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5
src/soc/mediatek/common/spi.c
View File

@ -43,8 +43,9 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks,
SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1,
SPI_CFG_SCK_HIGH, sck_ticks - 1);
SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly,
SPI_CFG1_CS_IDLE, cs_ticks - 1);
SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE, cs_ticks - 1);
SET32_BITFIELDS(&GET_TICK_DLY_REG(regs), SPI_TICK_DLY, tick_dly);
}
static void spi_sw_reset(struct mtk_spi_regs *regs)

3
src/soc/mediatek/mt8173/include/soc/spi.h
View File

@ -8,6 +8,7 @@
#define SPI_BUS_NUMBER 1
#define GET_SCK_REG(x) x->spi_cfg0_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0)
DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8)
@ -17,6 +18,6 @@ DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 24)
DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29)
#endif

4
src/soc/mediatek/mt8183/include/soc/spi.h
View File

@ -8,6 +8,7 @@
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
@ -18,7 +19,6 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29)
#endif

3
src/soc/mediatek/mt8186/include/soc/spi.h
View File

@ -13,6 +13,7 @@
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
@ -23,7 +24,7 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29)
enum {
SPI_NOR_GPIO_SET0 = 0,

3
src/soc/mediatek/mt8192/include/soc/spi.h
View File

@ -8,6 +8,7 @@
#define SPI_BUS_NUMBER 8
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
@ -18,6 +19,6 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29)
#endif

3
src/soc/mediatek/mt8195/include/soc/spi.h
View File

@ -8,6 +8,7 @@
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) x->spi_cfg2_reg
#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
@ -18,6 +19,6 @@ DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29)
#endif