AMD Bald Eagle: Add northbridge files for new AMD processor

Also fix a typo in a config option for SteppeEagle.

Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7247
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

src/include/device/pci_ids.h

@@ -286,10 +286,12 @@
 
 #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT	0x1600
 #define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT	0x1400
+#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT	0x141A
 #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT	0x1536
 #define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT  0x1566
 #define PCI_DEVICE_ID_AMD_10H_NB_HT		0x1200
 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU		0x1419
+#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU	0x1423
 
 #define PCI_DEVICE_ID_ATI_SB600_LPC		0x438D
 #define PCI_DEVICE_ID_ATI_SB600_SATA		0x4380

src/northbridge/amd/pi/00630F01/Kconfig

@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+config NORTHBRIDGE_AMD_PI_00630F01
+	bool
+	select MMCONF_SUPPORT
+	select PER_DEVICE_ACPI_TABLES
+
+if NORTHBRIDGE_AMD_PI_00630F01
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xF8000000
+
+config MMCONF_BUS_NUMBER
+	int
+	default 64
+
+config VGA_BIOS_ID
+	string
+	default "1002,1304"
+	help
+	  The default VGA BIOS PCI vendor/device ID should be set to the
+	  result of the map_oprom_vendev() function in northbridge.c.
+
+config VGA_BIOS_FILE
+	string
+	default "3rdparty/northbridge/amd/00630F01/VBIOS.bin"
+
+endif

src/northbridge/amd/pi/00630F01/Makefile.inc

@@ -0,0 +1,23 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += dimmSpd.c
+
+ramstage-y += iommu.c
+ramstage-y += northbridge.c

src/northbridge/amd/pi/00630F01/acpi/northbridge.asl

@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A03"))	/* PCI Express Root Bridge */
+Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+
+Method (_BBN, 0, NotSerialized)
+{
+	Return (Zero)
+}
+
+Method (_STA, 0, NotSerialized)
+{
+	Return (0x0B)
+}
+
+Method (_PRT, 0, NotSerialized)
+{
+	If (PMOD)
+	{
+		Return (APR0)
+	}
+
+	Return (PR0)
+}
+
+Device(AMRT) {
+	Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* Dev2 is also an external GFX bridge */
+Device(PBR2) {
+	Name(_ADR, 0x00020000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS2) }   /* APIC mode */
+		Return (PS2)                  /* PIC Mode */
+	} /* end _PRT */
+} /* end PBR2 */
+
+/* Dev3 GPP Root Port Bridge */
+Device(PBR3) {
+	Name(_ADR, 0x00030000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS3) }	/* APIC mode */
+		Return (PS3)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR3 */

src/northbridge/amd/pi/00630F01/chip.h

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESA_00630F01_CHIP_H_
+#define _AGESA_00630F01_CHIP_H_
+
+struct northbridge_amd_pi_00630F01_config
+{
+	u8 spdAddrLookup[1][2][2];
+};
+
+#endif

src/northbridge/amd/pi/00630F01/dimmSpd.c

@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/pci_def.h>
+#include <device/device.h>
+
+/* warning: Porting.h includes an open #pragma pack(1) */
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "chip.h"
+
+#include "northbridge/amd/pi/dimmSpd.h"
+
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+{
+	int spdAddress;
+	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	ROMSTAGE_CONST struct northbridge_amd_pi_00630F01_config *config = dev->chip_info;
+
+	if ((dev == 0) || (config == 0))
+		return AGESA_ERROR;
+
+	if (info->SocketId     >= DIMENSION(config->spdAddrLookup      ))
+		return AGESA_ERROR;
+	if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0]   ))
+		return AGESA_ERROR;
+	if (info->DimmId       >= DIMENSION(config->spdAddrLookup[0][0]))
+		return AGESA_ERROR;
+
+	spdAddress = config->spdAddrLookup
+		[info->SocketId] [info->MemChannelId] [info->DimmId];
+
+	if (spdAddress == 0)
+		return AGESA_ERROR;
+
+	int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
+	if (err)
+		return AGESA_ERROR;
+	return AGESA_SUCCESS;
+}

src/northbridge/amd/pi/00630F01/iommu.c

@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <lib.h>
+
+static void iommu_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, 0x44);
+	res->size = 512 * 1024;
+	res->align = log2(res->size);
+	res->gran = log2(res->size);
+	res->limit = 0xffffffff;	/* 4G */
+	res->flags = IORESOURCE_MEM;
+}
+
+static void iommu_set_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_set_resources(dev);
+
+	res = find_resource(dev, 0x44);
+	/* Remember this resource has been stored */
+	res->flags |= IORESOURCE_STORED;
+	/* For now, do only 32-bit space allocation */
+	pci_write_config32(dev, 0x48, 0x0);
+	pci_write_config32(dev, 0x44, res->base | (1 << 0));
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations iommu_ops = {
+	.read_resources = iommu_read_resources,
+	.set_resources = iommu_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver iommu_driver __pci_driver = {
+	.ops = &iommu_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU,
+};

src/northbridge/amd/pi/00630F01/northbridge.h

@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H
+#define NORTHBRIDGE_AMD_AGESA_FAM15H_H
+
+static struct device_operations pci_domain_ops;
+static struct device_operations cpu_bus_ops;
+
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */

src/northbridge/amd/pi/00630F01/pci_devs.h

@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AMD_00630F01_PCI_DEVS_H_
+#define _AMD_00630F01_PCI_DEVS_H_
+
+#define BUS0 0
+
+/* Graphics and Display */
+#define GFX_DEV 0x1
+#define GFX_FUNC 0
+#define GFX_DEVID 0x1304
+#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC)
+#define PIRQ_GFX	FCH_INT_TABLE_SIZE
+                            /* Integrated graphics device, must be after the
+                             * last C00/C01 entry
+                             */
+
+/* Internal Audio controller */
+#define ACTL_DEV 0x1
+#define ACTL_FUNC 1
+#define ACTL_DEVID 0x1308
+#define ACTL_DEVFN PCI_DEVFN(ACTL_DEV,ACTL_FUNC)
+#define PIRQ_ACTL	FCH_INT_TABLE_SIZE+1
+                            /* Integrated HDMI audio device, must be after the
+                             * last C00/C01 entry
+                             */
+
+/* PCIe Ports */
+#define NB_GFX_PCIE_PORTS_DEV 0x2
+#define NB_GPP_PCIE_PORTS_DEV 0x3
+#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x01)
+#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x02)
+#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x01)
+#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x02)
+#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x03)
+#define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x04)
+#define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x05)
+
+#endif /* _AMD_00630F01_PCI_DEVS_H_ */

src/northbridge/amd/pi/BiosCallOuts.h

@@ -24,7 +24,7 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
+#if CONFIG_NORTHBRIDGE_AMD_PI_00630F01 || CONFIG_NORTHBRIDGE_AMD_PI_00730F01
 
 #define BIOS_HEAP_START_ADDRESS 	0x010000000
 #define BIOS_HEAP_SIZE			0x30000

src/northbridge/amd/pi/Kconfig

@@ -32,6 +32,7 @@ config S3_VGA_ROM_RUN
 	bool
 	default n
 
+source src/northbridge/amd/pi/00630F01/Kconfig
 source src/northbridge/amd/pi/00730F01/Kconfig
 
 endif # NORTHBRIDGE_AMD_PI

src/northbridge/amd/pi/Makefile.inc

@@ -17,6 +17,7 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
 
 romstage-y += def_callouts.c

src/northbridge/amd/pi/agesawrapper.h

@@ -33,6 +33,7 @@ enum {
 	PICK_WHEA_CMC,  /* WHEA CMV table */
 	PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
 	PICK_IVRS,      /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */
+	PICK_CRAT,
 };
 
 AGESA_STATUS agesawrapper_amdinitreset(void);
@@ -54,5 +55,6 @@ AGESA_STATUS agesawrapper_fchs3earlyrestore(void);
 AGESA_STATUS agesawrapper_fchs3laterestore(void);
 
 VOID OemCustomizeInitEarly (IN	OUT AMD_EARLY_PARAMS *InitEarly);
+VOID amd_initcpuio(void);
 
 #endif /* _AGESAWRAPPER_H_ */

src/northbridge/amd/pi/def_callouts.c

@@ -110,8 +110,8 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt
 	pVbiosImageInfo->ImagePtr = cbfs_get_file_content(
 			CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom",
 			CBFS_TYPE_OPTIONROM, NULL);
-	/* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */
+	printk(BIOS_DEBUG, "agesa_GfxGetVbiosImage: IMGptr=%p\n", pVbiosImageInfo->ImagePtr);
-	return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS;
+	return (pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING);
 }
 
 AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)