soc/intel/skylake: Remove pad configuration size hardcoding

Existing GPIO driver inside coreboot use some hardcoded magic number
to calculate gpio pad offset. Avoid this kind of hardcoding.

Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/gpio.c

@@ -226,7 +226,8 @@ static void *gpio_dw_regs(gpio_t pad)
 	pad_relative = pad - comm->min;
 
 	/* DW0 and DW1 regs are 4 bytes each. */
-	return &regs[PAD_CFG_DW_OFFSET + pad_relative * 8];
+	return &regs[PAD_CFG_DW_OFFSET + pad_relative *
+			GPIO_DWx_SIZE(GPIO_DWx_COUNT)];
 }
 
 static void *gpio_hostsw_reg(gpio_t pad, size_t *bit)

src/soc/intel/skylake/include/soc/gpio.h

@@ -19,6 +19,8 @@
 
 #include <soc/gpio_defs.h>
 
+#define GPIO_DWx_SIZE(x)	(sizeof(uint32_t) * (x))
+
 #define CROS_GPIO_DEVICE_NAME	"INT344B:00"
 
 #ifndef __ACPI__

src/soc/intel/skylake/include/soc/gpio_defs.h

@@ -33,6 +33,7 @@
 #define GPIO_NUM_GROUPS		8
 #define GPIO_MAX_NUM_PER_GROUP	24
 
+#define GPIO_DWx_COUNT		2 /* DW0 and DW1 */
 /*
  * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
  */