soc/intel/skylake: Remove pad configuration size hardcoding
Existing GPIO driver inside coreboot use some hardcoded magic number to calculate gpio pad offset. Avoid this kind of hardcoding. Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -226,7 +226,8 @@ static void *gpio_dw_regs(gpio_t pad)
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pad_relative = pad - comm->min;
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/* DW0 and DW1 regs are 4 bytes each. */
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return ®s[PAD_CFG_DW_OFFSET + pad_relative * 8];
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return ®s[PAD_CFG_DW_OFFSET + pad_relative *
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GPIO_DWx_SIZE(GPIO_DWx_COUNT)];
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}
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static void *gpio_hostsw_reg(gpio_t pad, size_t *bit)
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@ -19,6 +19,8 @@
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#include <soc/gpio_defs.h>
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#define GPIO_DWx_SIZE(x) (sizeof(uint32_t) * (x))
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#define CROS_GPIO_DEVICE_NAME "INT344B:00"
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#ifndef __ACPI__
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@ -33,6 +33,7 @@
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#define GPIO_NUM_GROUPS 8
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#define GPIO_MAX_NUM_PER_GROUP 24
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#define GPIO_DWx_COUNT 2 /* DW0 and DW1 */
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/*
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* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
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*/
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