soc/intel/skylake: Remove pad configuration size hardcoding

Existing GPIO driver inside coreboot use some hardcoded magic number
to calculate gpio pad offset. Avoid this kind of hardcoding.

Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2016-11-23 00:54:47 +05:30 committed by Martin Roth
parent eedf6d8aa8
commit 0068dfdcc8
3 changed files with 5 additions and 1 deletions

View File

@ -226,7 +226,8 @@ static void *gpio_dw_regs(gpio_t pad)
pad_relative = pad - comm->min;
/* DW0 and DW1 regs are 4 bytes each. */
return &regs[PAD_CFG_DW_OFFSET + pad_relative * 8];
return &regs[PAD_CFG_DW_OFFSET + pad_relative *
GPIO_DWx_SIZE(GPIO_DWx_COUNT)];
}
static void *gpio_hostsw_reg(gpio_t pad, size_t *bit)

View File

@ -19,6 +19,8 @@
#include <soc/gpio_defs.h>
#define GPIO_DWx_SIZE(x) (sizeof(uint32_t) * (x))
#define CROS_GPIO_DEVICE_NAME "INT344B:00"
#ifndef __ACPI__

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@ -33,6 +33,7 @@
#define GPIO_NUM_GROUPS 8
#define GPIO_MAX_NUM_PER_GROUP 24
#define GPIO_DWx_COUNT 2 /* DW0 and DW1 */
/*
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
*/