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mb/google/puff: Update DPTF parameters for faffy 

1. TSRO trip point from 75C change to 73C
2. Sample period time from 5s change to 60s

BUG=b:160385395
BRANCH=puff
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0b000841845ce793be0e52fc28a07ac6a931ef7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
David Wu 2020-09-25 16:06:17 +08:00 committed by Edward O'Callaghan
parent 029069960e
commit 006acd3c28
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/hatch/variants/faffy/overridetree.cb
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@ -281,7 +281,7 @@ chip soc/intel/cannonlake
chip drivers/intel/dptf
## Passive Policy
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 73, 60000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"