soc/intel/common: Wrap lines at 80 columns

Fix the following error detected by checkpatch.pl:

ERROR: code indent should use tabs where possible

TEST=Build and run on Galileo Gen2

Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18753
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/common/acpi/acpi.c

@@ -71,7 +71,7 @@ __attribute__((weak)) uint32_t cpu_get_max_ratio(void)
 __attribute__((weak)) uint32_t cpu_get_bus_clock(void)
 {
 	/* CPU bus clock is set by default here to 100MHz.
-           This function returns the bus clock in KHz.
+	 * This function returns the bus clock in KHz.
 	 */
 	return 100 * KHz;
 }

src/soc/intel/common/gma.h

@@ -34,7 +34,7 @@ typedef struct {
 	u32	version;	    /* Offset 20   OpRegion structure version */
 	u8	sbios_version[32];  /* Offset 24   System BIOS build version */
 	u8	vbios_version[16];  /* Offset 56   Video BIOS build version */
-	u8	driver_version[16];	/* Offset 72   Graphic driver build version */
+	u8	driver_version[16]; /* Offset 72   Graphic drvr build version */
 	u32	mailboxes;	    /* Offset 88   Mailboxes supported */
 	u32	dmod;		    /* Offset 92   Driver Model */
 	u32	pcon;		    /* Offset 96   Platform Capabilities */
@@ -100,7 +100,9 @@ typedef struct {
 	u32	chpd;	/* Offset 168  Current hot plug enable indicator */
 	u32	clid;	/* Offset 172  Current lid state indicator */
 	u32	cdck;	/* Offset 176  Current docking state indicator */
-	u32	sxsw;		/* Offset 180  Display Switch notification on Sx State resume */
+	u32	sxsw;	/* Offset 180  Display Switch notification on Sx State
+			 * resume
+			 */
 	u32	evts;	/* Offset 184  Events supported by ASL */
 	u32	cnot;	/* Offset 188  Current OS Notification */
 	u32	nrdy;	/* Offset 192  Reasons for DRDY = 0 */
@@ -124,7 +126,7 @@ typedef struct {
 /* mailbox 2: software sci interface */
 typedef struct {
 	u32	scic;	/* Offset 0  Software SCI function number parameters */
-	u32	parm;		/* Offset 0    Software SCI function number parameters */
+	u32	parm;	/* Offset 4  Software SCI function number parameters */
 	u32	dslp;	/* Offset 8  Driver sleep timeout */
 	u8	reserved[244];	/* Offset 12   Reserved */
 } __attribute__((packed)) opregion_mailbox2_t;
@@ -138,11 +140,15 @@ typedef struct {
 	u32	bclp;		/* Offset 16  Backlight britness to set */
 	u32	pfit;		/* Offset 20  Panel fitting Request */
 	u32	cblv;		/* Offset 24  Brightness Current State */
-	u16	bclm[20];	/* Offset 28   Backlight Brightness Level Duty Cycle Mapping Table */
+	u16	bclm[20];	/* Offset 28  Backlight Brightness Level Duty
+				 *            Cycle Mapping Table
+				 */
 	u32	cpfm;		/* Offset 68  Panel Fitting Current Mode */
 	u32	epfm;		/* Offset 72  Enabled Panel Fitting Modes */
 	u8	plut[74];	/* Offset 76  Panel Look Up Table */
-	u32	pfmb;		/* Offset 150  PWM Frequency and Minimum Brightness */
+	u32	pfmb;		/* Offset 150 PWM Frequency and Minimum
+				 *            Brightness
+				 */
 	u32	ccdv;		/* Offset 154 Color Correction Default Values */
 	u32	pcft;		/* Offset 158 Power Conservation Features */
 	u32	srot;		/* Offset 162 Supported Rotation angle */
@@ -150,8 +156,12 @@ typedef struct {
 	u64	fdsp;		/* Offset 170 FFS Display Physical address */
 	u32	fdss;		/* Offset 178 FFS Display Size */
 	u32	stat;		/* Offset 182 State Indicator */
-	u64	rvda;		/* Offset 186  (Igd opregion offset 0x3BAh) Physical address of Raw VBT data */
+	u64	rvda;		/* Offset 186 (Igd opregion offset 0x3BAh)
-	u32	rvds;		/* Offset 194  (Igd opregion offset 0x3C2h) Size of Raw VBT data */
+				 *            Physical address of Raw VBT data
+				 */
+	u32	rvds;		/* Offset 194 (Igd opregion offset 0x3C2h)
+				 *            Size of Raw VBT data
+				 */
 	u8	reserved[58];	/* Offset 198 Reserved */
 } __attribute__((packed)) opregion_mailbox3_t;
 

src/soc/intel/common/smihandler.c

@@ -407,7 +407,8 @@ static uint64_t em64t100_smm_save_state_get_reg(void *state, enum smm_reg reg)
 	return value;
 }
 
-static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg, uint64_t val)
+static void em64t100_smm_save_state_set_reg(void *state, enum smm_reg reg,
+	uint64_t val)
 {
 	em64t100_smm_state_save_area_t *smm_state = state;
 	switch (reg) {
@@ -458,7 +459,8 @@ static uint64_t em64t101_smm_save_state_get_reg(void *state, enum smm_reg reg)
 	return value;
 }
 
-static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg, uint64_t val)
+static void em64t101_smm_save_state_set_reg(void *state, enum smm_reg reg,
+	uint64_t val)
 {
 	em64t101_smm_state_save_area_t *smm_state = state;
 	switch (reg) {