Intel cpus: add hyper-threading CPU support to new CAR
This improvement of CAR code starts the sibling CPU processors and clears their cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/604 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Kyösti Mälkki
Patrick Georgi
parent
05d6ffba0f
commit
0078ceb553
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@ -2,7 +2,9 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -25,6 +27,7 @@
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/* Macro to access Local APIC registers at default base. */
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#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
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#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff)
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#define CPU_MAXPHYADDR 36
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#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
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@ -41,12 +44,9 @@
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
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movl %eax, (%edi)
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/* Zero out all fixed range and variable range MTRRs. */
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/* Zero out all fixed range and variable range MTRRs.
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* For hyper-threaded CPU MTRRs are shared so we actually
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* clear them more than once, but we don't care. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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@ -59,12 +59,127 @@ clear_mtrrs:
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dec %edi
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jnz clear_mtrrs
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post_code(0x21)
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/* Configure the default memory type to uncacheable. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(0x22)
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/* Enable local apic. */
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movl $LAPIC_BASE_MSR, %ecx
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rdmsr
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andl $(~CPU_PHYSMASK_HI), %edx
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andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax
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orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax
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wrmsr
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andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
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jz ap_init
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bsp_init:
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post_code(0x23)
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/* Send INIT IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax
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1: movl %eax, (%edi)
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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movl (%edi), %ecx
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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post_code(0x24)
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/* For a hyper-threading processor, cache must not be disabled
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* on an AP on the same physical package with the BSP.
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*/
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movl $01, %eax
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cpuid
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btl $28, %edx
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jnc sipi_complete
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bswapl %ebx
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cmpb $01, %bh
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jbe sipi_complete
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hyper_threading_cpu:
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/* delay 10 ms */
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movl $10000, %ecx
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1: inb $0x80, %al
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dec %ecx
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jnz 1b
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post_code(0x25)
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/* Send Start IPI to all excluding ourself. */
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movl LAPIC(ICR), %edi
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movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax
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1: movl %eax, (%edi)
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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movl (%edi), %ecx
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andl $LAPIC_ICR_BUSY, %ecx
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jnz 1b
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/* delay 250 us */
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movl $250, %ecx
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1: inb $0x80, %al
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dec %ecx
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jnz 1b
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post_code(0x26)
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/* Wait for sibling CPU to start. */
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1: movl $(MTRRphysBase_MSR(0)), %ecx
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rdmsr
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andl %eax, %eax
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jnz sipi_complete
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movl $0x30, %ecx
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2: pause
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dec %ecx
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jnz 2b
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jmp 1b
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ap_init:
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post_code(0x27)
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/* Do not disable cache (so BSP can enable it). */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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movl %eax, %cr0
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post_code(0x28)
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/* MTRR registers are shared between HT siblings. */
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movl $(MTRRphysBase_MSR(0)), %ecx
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movl $(1<<12), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x29)
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ap_halt:
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cli
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1: hlt
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jnz 1b
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sipi_complete:
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post_code(0x2a)
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/* Set Cache-as-RAM base address. */
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movl $(MTRRphysBase_MSR(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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@ -83,6 +198,8 @@ clear_mtrrs:
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orl $MTRRdefTypeEn, %eax
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wrmsr
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post_code(0x2b)
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/* Enable L2 cache Write-Back (WBINVD and FLUSH#).
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*
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* MSR is set when DisplayFamily_DisplayModel is one of:
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@ -118,6 +235,8 @@ has_msr_11e:
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wrmsr
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no_msr_11e:
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post_code(0x2c)
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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@ -136,6 +255,8 @@ no_msr_11e:
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x2d)
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#if CONFIG_XIP_ROM_SIZE
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRRphysBase_MSR(1), %ecx
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@ -160,6 +281,8 @@ no_msr_11e:
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andl $(~((1 << 30) | (1 << 29))), %eax
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movl %eax, %cr0
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post_code(0x2e)
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/* Set up the stack pointer. */
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#if CONFIG_USBDEBUG
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/* Leave some space for the struct ehci_debug_info. */
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@ -173,14 +296,12 @@ no_msr_11e:
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movl %esp, %ebp
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pushl %eax
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post_code(0x23)
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post_code(0x2f)
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/* Call romstage.c main function. */
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call main
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addl $4, %esp
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post_code(0x2f)
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post_code(0x30)
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/* Disable cache. */
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@ -188,7 +309,7 @@ no_msr_11e:
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x31)
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post_code(0x34)
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/* Disable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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@ -196,18 +317,18 @@ no_msr_11e:
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andl $(~MTRRdefTypeEn), %eax
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wrmsr
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post_code(0x31)
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post_code(0x35)
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invd
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post_code(0x33)
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post_code(0x36)
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/* Enable cache. */
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movl %cr0, %eax
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andl $~((1 << 30) | (1 << 29)), %eax
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movl %eax, %cr0
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post_code(0x36)
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post_code(0x37)
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/* Disable cache. */
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movl %cr0, %eax
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