nb/intel/gm45: Correctly cache TSEG
Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -434,7 +434,6 @@ void gm45_late_init(stepping_t);
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u32 decode_igd_memory_size(u32 gms);
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u32 decode_igd_memory_size(u32 gms);
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u32 decode_igd_gtt_size(u32 gsm);
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u32 decode_igd_gtt_size(u32 gsm);
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u32 decode_tseg_size(u8 esmramc);
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u32 decode_tseg_size(u8 esmramc);
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uintptr_t smm_region_start(void);
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void init_iommu(void);
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void init_iommu(void);
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@ -221,22 +221,6 @@ static const char *northbridge_acpi_name(const struct device *dev)
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return NULL;
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return NULL;
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}
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}
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u32 northbridge_get_tseg_base(void)
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{
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return (u32)smm_region_start();
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}
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u32 northbridge_get_tseg_size(void)
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{
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struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (dev == NULL)
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die("could not find pci 00:00.0!\n");
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const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
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return decode_tseg_size(esmramc) << 10;
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}
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void northbridge_write_smram(u8 smram)
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void northbridge_write_smram(u8 smram)
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{
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{
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struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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@ -26,6 +26,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mtrr.h>
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#include <cbmem.h>
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#include <cbmem.h>
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#include <program_loading.h>
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#include <program_loading.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include "gm45.h"
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#include "gm45.h"
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/*
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/*
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@ -83,7 +84,7 @@ u32 decode_tseg_size(u8 esmramc)
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}
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}
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}
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}
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uintptr_t smm_region_start(void)
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u32 northbridge_get_tseg_base(void)
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{
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{
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const pci_devfn_t dev = PCI_DEV(0, 0, 0);
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const pci_devfn_t dev = PCI_DEV(0, 0, 0);
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@ -106,13 +107,19 @@ uintptr_t smm_region_start(void)
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return tor;
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return tor;
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}
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}
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u32 northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
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return decode_tseg_size(esmramc) << 10;
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}
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/* Depending of UMA and TSEG configuration, TSEG might start at any
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/* Depending of UMA and TSEG configuration, TSEG might start at any
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* CBMEM top downwards to 4 MiB boundary.
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* CBMEM top downwards to 4 MiB boundary.
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*/
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*/
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void *cbmem_top(void)
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void *cbmem_top(void)
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{
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{
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uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
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uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
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return (void *) top_of_ram;
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return (void *) top_of_ram;
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}
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}
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@ -135,12 +142,14 @@ void platform_enter_postcar(void)
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache a 8 MiB region below the top of ram and 8 MiB above top of
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/* Cache 8 MiB region below the top of ram and 2 MiB above top of
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* ram to cover both cbmem as the TSEG region.
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* ram to cover both cbmem as the TSEG region.
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*/
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*/
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top_of_ram = (uintptr_t)cbmem_top();
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
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northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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run_postcar_phase(&pcf);
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