soc/amd/picasso: supply SMBIOS type 17
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables. BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Rob Barnes
Aaron Durbin
parent
33d9eeae5f
commit
009a23d5c8
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@ -79,6 +79,7 @@ ramstage-y += update_microcode.c
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ramstage-y += graphics.c
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ramstage-y += graphics.c
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ramstage-y += pcie_gpp.c
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ramstage-y += pcie_gpp.c
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ramstage-y += xhci.c
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ramstage-y += xhci.c
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ramstage-y += dmi.c
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smm-y += smihandler.c
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smm-y += smihandler.c
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smm-y += smi_util.c
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smm-y += smi_util.c
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@ -0,0 +1,195 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/**
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* This code was adapted from src/soc/amd/common/block/pi/amd_late_init.c
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*/
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#include <fsp/util.h>
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#include <memory_info.h>
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#include <console/console.h>
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#include <cbmem.h>
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#include <string.h>
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#include <ec/google/chromeec/ec.h>
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#include <bootstate.h>
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#include <lib.h>
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#include <dimm_info_util.h>
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#include <vendorcode/amd/fsp/picasso/dmi_info.h>
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/**
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* Populate dimm_info using AGESA TYPE17_DMI_INFO.
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*/
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static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17,
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struct dimm_info *dimm)
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{
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hexstrtobin(dmi17->SerialNumber, dimm->serial, sizeof(dimm->serial));
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dimm->dimm_size = smbios_memory_size_to_mib(dmi17->MemorySize, dmi17->ExtSize);
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dimm->ddr_type = dmi17->MemoryType;
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dimm->ddr_frequency = dmi17->Speed;
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dimm->rank_per_dimm = dmi17->Attributes;
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dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->FormFactor);
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dimm->bus_width =
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smbios_bus_width_to_spd_width(dmi17->TotalWidth, dmi17->DataWidth);
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dimm->mod_id = dmi17->ManufacturerIdCode;
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dimm->bank_locator = 0;
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strncpy((char *)dimm->module_part_number, dmi17->PartNumber,
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sizeof(dimm->module_part_number) - 1);
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}
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static void print_dimm_info(const struct dimm_info *dimm)
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{
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printk(BIOS_DEBUG,
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"CBMEM_ID_MEMINFO:\n"
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" dimm_size: %u\n"
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" ddr_type: 0x%hx\n"
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" ddr_frequency: %hu\n"
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" rank_per_dimm: %hhu\n"
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" channel_num: %hhu\n"
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" dimm_num: %hhu\n"
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" bank_locator: %hhu\n"
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" mod_id: %hx\n"
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" mod_type: 0x%hhx\n"
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" bus_width: %hhu\n"
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" serial: %02hhx%02hhx%02hhx%02hhx\n"
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" module_part_number(%zu): %s\n",
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dimm->dimm_size,
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dimm->ddr_type,
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dimm->ddr_frequency,
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dimm->rank_per_dimm,
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dimm->channel_num,
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dimm->dimm_num,
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dimm->bank_locator,
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dimm->mod_id,
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dimm->mod_type,
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dimm->bus_width,
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dimm->serial[0],
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dimm->serial[1],
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dimm->serial[2],
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dimm->serial[3],
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strlen((const char *)dimm->module_part_number),
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(char *)dimm->module_part_number);
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}
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static void print_dmi_info(const TYPE17_DMI_INFO *dmi17)
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{
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printk(BIOS_DEBUG,
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"AGESA TYPE 17 DMI INFO:\n"
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" Handle: %hu\n"
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" TotalWidth: %hu\n"
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" DataWidth: %hu\n"
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" MemorySize: %hu\n"
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" DeviceSet: %hhu\n"
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" Speed: %hu\n"
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" ManufacturerIdCode: %llx\n"
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" Attributes: %hhu\n"
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" ExtSize: %u\n"
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" ConfigSpeed: %hu\n"
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" MemoryType: 0x%x\n"
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" FormFactor: 0x%x\n"
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" DeviceLocator: %8s\n"
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" BankLocator: %10s\n"
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" SerialNumber(%zu): %9s\n"
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" PartNumber(%zu): %19s\n",
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dmi17->Handle,
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dmi17->TotalWidth,
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dmi17->DataWidth,
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dmi17->MemorySize,
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dmi17->DeviceSet,
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dmi17->Speed,
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dmi17->ManufacturerIdCode,
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dmi17->Attributes,
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dmi17->ExtSize,
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dmi17->ConfigSpeed,
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dmi17->MemoryType,
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dmi17->FormFactor,
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dmi17->DeviceLocator,
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dmi17->BankLocator,
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strlen((const char *)dmi17->SerialNumber),
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dmi17->SerialNumber,
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strlen((const char *)dmi17->PartNumber),
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dmi17->PartNumber);
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}
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/**
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* Marshalls dimm info from AMD_FSP_DMI_HOB into CBMEM_ID_MEMINFO
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*/
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static void prepare_dmi_17(void *unused)
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{
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const DMI_INFO *dmi_table;
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const TYPE17_DMI_INFO *type17_dmi_info;
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struct memory_info *mem_info;
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struct dimm_info *dimm_info;
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char cbi_part_number[DIMM_INFO_PART_NUMBER_SIZE];
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bool use_cbi_part_number = false;
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size_t dimm_cnt = 0;
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size_t amd_fsp_dmi_hob_size;
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const EFI_GUID amd_fsp_dmi_hob_guid = AMD_FSP_DMI_HOB_GUID;
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printk(BIOS_DEBUG, "Saving dimm info for smbios type 17\n");
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/* Allocate meminfo in cbmem. */
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mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
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if (!mem_info) {
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printk(BIOS_ERR,
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"Failed to add memory info to CBMEM, DMI tables will be incomplete\n");
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return;
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}
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memset(mem_info, 0, sizeof(struct memory_info));
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/* Locate the memory info HOB. */
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dmi_table = fsp_find_extension_hob_by_guid(
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(const uint8_t *)&amd_fsp_dmi_hob_guid, &amd_fsp_dmi_hob_size);
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if (dmi_table == NULL || amd_fsp_dmi_hob_size == 0) {
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printk(BIOS_ERR,
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"AMD_FSP_DMI_HOB not found, DMI table 17 will be incomplete\n");
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return;
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}
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printk(BIOS_DEBUG, "AMD_FSP_DMI_HOB found\n");
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if (CONFIG(CHROMEOS)) {
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/* Prefer DRAM part number from CBI. */
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if (google_chromeec_cbi_get_dram_part_num(
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cbi_part_number, sizeof(cbi_part_number)) == 0) {
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use_cbi_part_number = true;
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} else {
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printk(BIOS_ERR, "Could not obtain DRAM part number from CBI\n");
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}
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}
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for (unsigned int channel = 0; channel < MAX_CHANNELS_PER_SOCKET; channel++) {
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for (unsigned int dimm = 0; dimm < MAX_DIMMS_PER_CHANNEL; dimm++) {
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type17_dmi_info = &dmi_table->T17[0][channel][dimm];
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/* DIMMs that are present will have a non-zero
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handle. */
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if (type17_dmi_info->Handle == 0)
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continue;
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print_dmi_info(type17_dmi_info);
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dimm_info = &mem_info->dimm[dimm_cnt];
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dimm_info->channel_num = channel;
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dimm_info->dimm_num = channel;
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transfer_memory_info(type17_dmi_info, dimm_info);
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if (use_cbi_part_number) {
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/* mem_info is memset to 0 above, so it's
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safe to assume module_part_number will be
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null terminated */
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strncpy((char *)dimm_info->module_part_number, cbi_part_number,
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sizeof(dimm_info->module_part_number) - 1);
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}
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print_dimm_info(dimm_info);
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dimm_cnt++;
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}
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}
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mem_info->dimm_cnt = dimm_cnt;
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}
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/* AMD_FSP_DMI_HOB is initialized very late, so check it just in time for writing tables. */
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BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, prepare_dmi_17, NULL);
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