mb/google/drallion: Enable HDA for drallion platform

Enable PchHdaIDispCodecDisconnect and
PchHdaAudioLinkHda for drallion variants.
This is needed with FSP 1263.

Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb

@@ -50,6 +50,10 @@ chip soc/intel/cannonlake
 	# Enable DDC for DDI port B
 	register "DdiPortBDdc" = "1"
 
+	# Disable iDisplay codec enumeration
+	register "PchHdaIDispCodecDisconnect" = "1"
+	register "PchHdaAudioLinkHda" = "1"
+
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
 	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -50,6 +50,10 @@ chip soc/intel/cannonlake
 	# Enable DDC for DDI port B
 	register "DdiPortBDdc" = "1"
 
+	# Disable iDisplay codec enumeration
+	register "PchHdaIDispCodecDisconnect" = "1"
+	register "PchHdaAudioLinkHda" = "1"
+
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
 	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |

src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb

@@ -56,6 +56,10 @@ chip soc/intel/cannonlake
 	register "LanWakeFromDeepSx" = "0"
 	register "WolEnableOverride" = "0"
 
+	# Disable iDisplay codec enumeration
+	register "PchHdaIDispCodecDisconnect" = "1"
+	register "PchHdaAudioLinkHda" = "1"
+
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
 	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |