mb/google/drallion: Enable HDA for drallion platform

Enable PchHdaIDispCodecDisconnect and
PchHdaAudioLinkHda for drallion variants.
This is needed with FSP 1263.

Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aamir Bohra 2019-08-23 10:32:56 -07:00 committed by Patrick Georgi
parent 5b549f3770
commit 00ad48554a
3 changed files with 12 additions and 0 deletions

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@ -50,6 +50,10 @@ chip soc/intel/cannonlake
# Enable DDC for DDI port B
register "DdiPortBDdc" = "1"
# Disable iDisplay codec enumeration
register "PchHdaIDispCodecDisconnect" = "1"
register "PchHdaAudioLinkHda" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |

View File

@ -50,6 +50,10 @@ chip soc/intel/cannonlake
# Enable DDC for DDI port B
register "DdiPortBDdc" = "1"
# Disable iDisplay codec enumeration
register "PchHdaIDispCodecDisconnect" = "1"
register "PchHdaAudioLinkHda" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |

View File

@ -56,6 +56,10 @@ chip soc/intel/cannonlake
register "LanWakeFromDeepSx" = "0"
register "WolEnableOverride" = "0"
# Disable iDisplay codec enumeration
register "PchHdaIDispCodecDisconnect" = "1"
register "PchHdaAudioLinkHda" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |