buildsystem: Make CPU microcode updating more configurable

This patch aims to improve the microcode in CBFS handling that was
brought by the last patches from Stefan and the Chromium team.

Choices in Kconfig
  - 1) Generate microcode from tree (default)
  - 2) Include external microcode file
  - 3) Do not put microcode in CBFS

The idea is to give the user full control over including non-free
blobs in the final ROM image.

MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode
is handled by a special class, cpu_microcode, as such:

cpu_microcode-y += microcode_file.c

MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is
needed by intel microcode updating. Once all intel cpus are converted to
cbfs updating, this variable can go away.

These files are then compiled and assembled into a binary CBFS file.
The advantage of doing it this way versus the current method is that
  1) The rule is CPU-agnostic
  2) Gives user more control over if and how to include microcode blobs
  3) The rules for building the microcode binary are kept in
   src/cpu/Makefile.inc, and thus would not clobber the other makefiles,
   which are already overloaded and very difficult to navigate.

Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1245
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Alexandru Gagniuc 2012-07-20 00:11:21 -05:00
parent eb1d39bac4
commit 00b579a447
10 changed files with 150 additions and 45 deletions

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@ -59,7 +59,7 @@ subdirs-y += site-local
#######################################################################
# Add source classes and their build options
classes-y := ramstage romstage driver smm
classes-y := ramstage romstage driver smm cpu_microcode
romstage-c-ccopts:=-D__PRE_RAM__
romstage-S-ccopts:=-D__PRE_RAM__

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@ -1,6 +1,8 @@
################################################################################
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2009 Ronald G. Minnich
##
@ -17,8 +19,8 @@
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
################################################################################
#######################################################################
# Take care of subdirectories
subdirs-y += boot
# subdirs-y += init
@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa
OPTION_TABLE_H:=$(obj)/option_table.h
endif
ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
cbfs-files-y += microcode_blob.bin
microcode_blob.bin-file = $(obj)/microcode_blob.bin
microcode_blob.bin-type = 0x53
endif
#######################################################################
################################################################################
# Build the final rom image
COREBOOT_ROM_DEPENDENCIES:=
ifeq ($(CONFIG_PAYLOAD_ELF),y)
@ -125,7 +121,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg
bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
bootsplash.jpg-type := bootsplash
#######################################################################
################################################################################
# i386 specific tools
NVRAMTOOL:=$(objutil)/nvramtool/nvramtool
@ -137,7 +133,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l
@printf " OPTION $(subst $(obj)/,,$(@))\n"
$(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@
#######################################################################
################################################################################
# Common recipes for all stages
$(objcbfs)/%.bin: $(objcbfs)/%.elf
@ -152,7 +148,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
$(OBJCOPY) --add-gnu-debuglink=$< $@.tmp
mv $@.tmp $@
#######################################################################
################################################################################
# Build the coreboot_ram (stage 2)
$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld
@ -176,7 +172,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs)
rm -f $@
$(AR) cr $@ $^
#######################################################################
################################################################################
# Ramstage for AP CPU (AMD K8, obsolete?)
$(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb
@ -187,7 +183,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@
#######################################################################
################################################################################
# done
crt0s = $(src)/arch/x86/init/prologue.inc
@ -268,7 +264,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
endif
#######################################################################
################################################################################
# Build the final rom image
$(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL)
@ -278,7 +274,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL
$(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt)
mv $@.tmp $@
#######################################################################
################################################################################
# Build the bootblock
bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb
@ -335,7 +331,7 @@ else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $<
endif
#######################################################################
################################################################################
# Build the romstage
$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld

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@ -62,10 +62,90 @@ config SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
config MICROCODE_IN_CBFS
bool "Look for microcode in CBFS"
default n
help
Load microcode updates from CBFS instead of compiling them in.
endif # ARCH_X86
config CPU_MICROCODE_IN_CBFS
bool
default n
choice
prompt "Include CPU microcode in CBFS"
default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS
default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS
config CPU_MICROCODE_CBFS_GENERATE
bool "Generate from tree"
help
Select this option if you want microcode updates to be assembled when
building coreboot and included in the final image as a separate CBFS
file. Microcode will not be hard-coded into ramstage.
The microcode file and may be removed from the ROM image at a later
time with cbfstool, if desired.
If unsure, select this option.
config CPU_MICROCODE_CBFS_EXTERNAL
bool "Include external microcode file"
help
Select this option if you want to include an external file containing
the CPU microcode. This will be included as a separate file in CBFS.
A word of caution: only select this option if you are sure the
microcode that you have is newer than the microcode shipping with
coreboot.
The microcode file and may be removed from the ROM image at a later
time with cbfstool, if desired.
If unsure, select "Generate from tree"
config CPU_MICROCODE_FILE
string "Path and filename of CPU microcode"
depends on CPU_MICROCODE_CBFS_EXTERNAL
default "cpu_microcode.bin"
help
The path and filename of the file containing the CPU microcode.
config CPU_MICROCODE_CBFS_NONE
bool "Do not include microcode updates"
help
Select this option if you do not want CPU microcode included in CBFS.
Note that for some CPUs, the microcode is hard-coded into the source
tree and is not loaded from CBFS. In this case, microcode will still
be updated. There is a push to move all microcode to CBFS, but this
change is not implemented for all CPUs.
This option currently applies to:
- Intel SandyBridge/IvyBridge
- VIA Nano
Microcode may be added to the ROM image at a later time with cbfstool,
if desired.
If unsure, select "Generate from tree"
The GOOD:
Microcode updates intend to solve issues that have been discovered
after CPU production. The expected effect is that systems work as
intended with the updated microcode, but we have also seen cases where
issues were solved by not applying microcode updates.
The BAD:
Note that some operating system include these same microcode patches,
so you may need to also disable microcode updates in your operating
system for this option to have an effect.
The UGLY:
A word of CAUTION: some CPUs depend on microcode updates to function
correctly. Not updating the microcode may leave the CPU operating at
less than optimal performance, or may cause outright hangups.
There are CPUs where coreboot cannot properly initialize the CPU
without microcode updates
For example, if running with the factory microcode, some Intel
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
will hang when changing the frequency.
Make sure you have a way of flashing the ROM externally before
selecting this option.
endchoice

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@ -1,3 +1,40 @@
################################################################################
## Subdirectories
################################################################################
subdirs-y += amd
subdirs-y += intel
subdirs-y += via
################################################################################
## Rules for building the microcode blob in CBFS
################################################################################
ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y)
cbfs-files-y += cpu_microcode_blob.bin
cpu_microcode_blob.bin-type = 0x53
# External microcode file, or are we generating one ?
ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y)
cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
else
cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin
endif
# In case we have more than one "source" (cough) files containing microcode, we
# Link them together in one large blob, so that we get all the microcode updates
# in one file. This makes it easier for objcopy in the final step.
# The --entry=0 is just here to suppress the LD warning. It does not affect the
# final microcode file.
$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs)
@printf " LD $(subst $(obj)/,,$(@))\n"
$(LD) -static --entry=0 $< -o $@
# We have a lot of useless data in the large blob, and we are only interested in
# the data section, so we only copy that part to the final microcode file
$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o
@printf " MICROCODE $(subst $(obj)/,,$(@))\n"
$(OBJCOPY) -j .data -O binary $< $@
endif

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@ -1,15 +1,5 @@
ramstage-y += microcode.c
ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
SRC_PATH = src/cpu/intel/microcode
FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
$(CC) $(FLAGS) -MMD -c -o $@ $<
$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
objcopy -j .data -O binary $< $@
-include $(obj)/microcode_blob.d
endif
################################################################################
## One small file with the awesome super-power of updating the cpu microcode
## directly from CBFS. You have been WARNED!!!
################################################################################
ramstage-y += microcode.c

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@ -28,7 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
#if CONFIG_MICROCODE_IN_CBFS
#if CONFIG_CPU_MICROCODE_IN_CBFS
#ifdef __PRE_RAM__
#include <arch/cbfs.h>
#else
@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void)
return msr.hi;
}
#if CONFIG_MICROCODE_IN_CBFS
#if CONFIG_CPU_MICROCODE_IN_CBFS
static
#endif
void intel_update_microcode(const void *microcode_updates)
@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates)
}
}
#if CONFIG_MICROCODE_IN_CBFS
#if CONFIG_CPU_MICROCODE_IN_CBFS
#define MICROCODE_CBFS_FILE "microcode_blob.bin"
#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin"
void intel_update_microcode_from_cbfs(void)
{

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@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
select MICROCODE_IN_CBFS
select CPU_MICROCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE

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@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc

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@ -18,5 +18,5 @@
*/
unsigned microcode[] = {
#include <microcode_blob.h>
#include "microcode_blob.h"
};

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@ -21,7 +21,7 @@
#define __CPU__INTEL__MICROCODE__
#ifndef __PRE_RAM__
#if CONFIG_MICROCODE_IN_CBFS
#if CONFIG_CPU_MICROCODE_IN_CBFS
void intel_update_microcode_from_cbfs(void);
#else
void intel_update_microcode(const void *microcode_updates);