soc/intel/common/block: Move smihandler common functions into common code
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
parent
e5c1aa69c7
commit
00b7533629
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright (C) 2015-2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -34,16 +34,6 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void)
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return &em64t100_smm_ops;
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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const smi_handler_t southbridge_smi[32] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2017 Intel Corporation.
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* Copyright (C) 2017-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,26 +17,19 @@
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/smihandler.h>
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#include <soc/p2sb.h>
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#include <soc/soc_chip.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include "chip.h"
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#define CSME0_FBE 0xf
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#define CSME0_BAR 0x0
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#define CSME0_FID 0xb0
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const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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static void pch_disable_heci(void)
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{
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struct pcr_sbi_msg msg = {
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@ -85,36 +78,6 @@ void smihandler_soc_at_finalize(void)
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pch_disable_heci();
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}
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void smihandler_soc_check_illegal_access(uint32_t tco_sts)
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{
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if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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@ -156,15 +156,6 @@ void smihandler_soc_at_finalize(void);
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*/
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int smihandler_soc_disable_busmaster(pci_devfn_t dev);
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void);
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/*
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* SoC needs to implement the mechanism to know if an illegal attempt
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* has been made to write to the BIOS area.
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*/
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void smihandler_soc_check_illegal_access(uint32_t tco_sts);
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/* Mainboard overrides. */
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/* Mainboard handler for GPI SMIs */
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2017 Intel Corp.
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* Copyright (C) 2015-2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -44,6 +44,11 @@ static struct global_nvs_t *gnvs;
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/* SoC overrides. */
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__weak const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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/* Specific SOC SMI handler during ramstage finalize phase */
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__weak void smihandler_soc_at_finalize(void)
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{
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@ -55,20 +60,29 @@ __weak int smihandler_soc_disable_busmaster(pci_devfn_t dev)
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return 1;
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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__weak uint32_t smihandler_soc_get_sci_mask(void)
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{
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return 0; /* No valid SCI mask for SMI handler */
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}
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/*
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* Needs to implement the mechanism to know if an illegal attempt
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* has been made to write to the BIOS area.
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*/
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__weak void smihandler_soc_check_illegal_access(
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static void smihandler_soc_check_illegal_access(
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uint32_t tco_sts)
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{
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return;
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if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* Mainboard overrides. */
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@ -472,6 +486,16 @@ void smihandler_southbridge_espi(
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mainboard_smi_espi_handler();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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static uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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void southbridge_smi_handler(void)
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{
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int i;
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corp.
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* Copyright (C) 2018-2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -15,25 +15,19 @@
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/smihandler.h>
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#include <soc/p2sb.h>
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#include <soc/soc_chip.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/soc_chip.h>
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#define CSME0_FBE 0xf
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#define CSME0_BAR 0x0
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#define CSME0_FID 0xb0
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const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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static void pch_disable_heci(void)
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{
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struct pcr_sbi_msg msg = {
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@ -82,36 +76,6 @@ void smihandler_soc_at_finalize(void)
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pch_disable_heci();
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}
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void smihandler_soc_check_illegal_access(uint32_t tco_sts)
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{
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if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2017 Intel Corporation.
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* Copyright (C) 2015-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -15,46 +15,9 @@
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/smihandler.h>
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#include <soc/pm.h>
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const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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void smihandler_soc_check_illegal_access(uint32_t tco_sts)
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{
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if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corp.
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* Copyright (C) 2019-2020 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -15,25 +15,19 @@
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/smihandler.h>
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#include <soc/p2sb.h>
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#include <soc/soc_chip.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/soc_chip.h>
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#define CSME0_FBE 0xf
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#define CSME0_BAR 0x0
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#define CSME0_FID 0xb0
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const struct smm_save_state_ops *get_smm_save_state_ops(void)
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{
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return &em64t101_smm_ops;
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}
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static void pch_disable_heci(void)
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{
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struct pcr_sbi_msg msg = {
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@ -82,36 +76,6 @@ void smihandler_soc_at_finalize(void)
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pch_disable_heci();
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}
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void smihandler_soc_check_illegal_access(uint32_t tco_sts)
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{
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if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM)
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&& fast_spi_wpd_status()))
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return;
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/*
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* BWE is RW, so the SMI was caused by a
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* write to BWE, not by a write to the BIOS
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*
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* This is the place where we notice someone
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* is trying to tinker with the BIOS. We are
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* trying to be nice and just ignore it. A more
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* resolute answer would be to power down the
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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fast_spi_enable_wp();
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}
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/* SMI handlers that should be serviced in SCI mode too. */
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uint32_t smihandler_soc_get_sci_mask(void)
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{
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uint32_t sci_mask =
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SMI_HANDLER_SCI_EN(APM_STS_BIT) |
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SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
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return sci_mask;
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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